ASRock Z490M Pro4 User Manual - Page 65

Contorl Slew Rate

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Z490M Pro4 Command Driving Adjust Command Driving for better signal. Default is 20. Control Driving Adjust Control Driving for better signal. Default is 20. Clock Driving Adjust Clock Driving for better signal. Default is 26. DQ Slew Rate Adjust DQ Slew Rate for better signal. Default is 59. Command Slew Rate Adjust Command Slew Rate for better signal. Default is 53 for IN, 89 for 2N. Contorl Slew Rate Adjust Control Slew Rate for better signal. Default is 53. Clock Slew Rate Adjust Clock Slew Rate for better signal. Default is 53. Dll Bandwidth 0 Configure Dll Bandwidth 0 (1067 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 1 Configure Dll Bandwidth 1 (1333 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 2 Configure Dll Bandwidth 2 (1600 MHz) to maximize the performance of intergrated memory controller. Dll Bandwidth 3 Configure Dll Bandwidth 3 (1867 MHz) to maximize the performance of intergrated memory controller. MRS Setting MRS tCL Configure the tCL for Memory MRS MR0. 59 English

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59
English
Z490M Pro4
Command Driving
Adjust Command Driving for better signal. Default is 20.
Control Driving
Adjust Control Driving for better signal. Default is 20.
Clock Driving
Adjust Clock Driving for better signal. Default is 26.
DQ Slew Rate
Adjust DQ Slew Rate for better signal. Default is 59.
Command Slew Rate
Adjust Command Slew Rate for better signal. Default is 53 for IN, 89 for 2N.
Contorl Slew Rate
Adjust Control Slew Rate for better signal. Default is 53.
Clock Slew Rate
Adjust Clock Slew Rate for better signal. Default is 53.
Dll Bandwidth 0
Configure Dll Bandwidth 0 (1067 MHz) to maximize the performance of
intergrated memory controller.
Dll Bandwidth 1
Configure Dll Bandwidth 1 (1333 MHz) to maximize the performance of intergrated
memory controller.
Dll Bandwidth 2
Configure Dll Bandwidth 2 (1600 MHz) to maximize the performance of
intergrated memory controller.
Dll Bandwidth 3
Configure Dll Bandwidth 3 (1867 MHz) to maximize the performance of intergrated
memory controller.
MRS Setting
MRS tCL
Configure the tCL for Memory MRS MR0.