ASRock Z690M-ITX/ax User Manual - Page 63

GT Unlimited Current Limit, DRAM Timing Configuration

Page 63 highlights

Z690M-ITX/ax Enabled. CPU Core Current Limit Configure the current limit of the CPU core. A lower limit can protect the CPU and save power, while a higher limit may improve performance. GT Unlimited Current Limit To unlock voltage regulator current limit completely, you can set this option to Enabled. GT Current Limit Configure the current limit of the GT slice. A lower limit can protect the CPU and save power, while a higher limit may improve performance. DRAM Configuration Memory Information Allows users to browse the serial presence detect (SPD) and Intel extreme memory profile (XMP) for DDR4 modules. DRAM Timing Configuration DRAM Reference Clock Select Auto for optimized settings. DRAM Frequency If [Auto] is selected, the motherboard will detect the memory module(s) inserted and assign the appropriate frequency automatically. DRAM Gear Mode High gear is good for high frequency. BCLK Frequency Configure the BCLK Frequency. Primary Timing CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. 55 English

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55
English
Z690M-ITX/ax
Enabled.
CPU Core Current Limit
Configure the current limit of the CPU core. A lower limit can protect the CPU and
save power, while a higher limit may improve performance.
GT Unlimited Current Limit
To unlock voltage regulator current limit completely, you can set this option to
Enabled.
GT Current Limit
Configure the current limit of the GT slice. A lower limit can protect the CPU and
save power, while a higher limit may improve performance.
DRAM Configuration
Memory Information
Allows users to browse the serial presence detect (SPD) and Intel extreme memory profile
(XMP) for DDR4 modules.
DRAM Timing Configuration
DRAM Reference Clock
Select Auto for optimized settings.
DRAM Frequency
If [Auto] is selected, the motherboard will detect the memory module(s) inserted
and assign the appropriate frequency automatically.
DRAM Gear Mode
High gear is good for high frequency.
BCLK Frequency
Configure the BCLK Frequency.
Primary Timing
CAS# Latency (tCL)
°e time between sending a column address to the memory and the beginning of the data
in response.