ASRock Z77TM-ITX User Manual - Page 51

CPU Thermal Throttling, No-Execute Memory Protection, Intel Virtualization Technology, Hardware

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Page 51 highlights

CPU Thermal Throttling Use this to enable CPU internal thermal control mechanism to keep the CPU from overheated. The default value is [Enabled]. No-Execute Memory Protection No-Execution (NX) Memory Protection Technology is an enhancement to the IA-32 Intel Architecture. An IA-32 processor with "No Execute (NX) Memory Protection" can prevent data pages from being used by malicious software to execute codes. This option will be hidden if the current CPU does not support No-Excute Memory Protection. Intel Virtualization Technology When this option is set to [Enabled], a VMM (Virtual Machine Architecture) can utilize the additional hardware capabilities provided by Vanderpool Technology. This option will be hidden if the installed CPU does not support Intel Virtualization Technology. Hardware Prefetcher Use this turn on/off the MLC streamer prefetcher. Adjacent Cache Line Prefetch Use this to turn on/off prefetching of adjacent cache lines. 51

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CPU Thermal Throttling
Use this to enable CPU internal thermal control mechanism to keep
the CPU from overheated. The default value is [Enabled].
No-Execute Memory Protection
No-Execution (NX) Memory Protection Technology is an enhance
-
ment to the IA-32 Intel Architecture. An IA-32 processor with “No
Execute (NX) Memory Protection” can prevent data pages from
being used by malicious software to execute codes. This option will
be hidden if the current CPU does not support No-Excute Memory
Protection.
Intel Virtualization Technology
When this option is set to [Enabled], a VMM (Virtual Machine Archi-
tecture) can utilize the additional hardware capabilities provided by
Vanderpool Technology. This option will be hidden if the installed
CPU does not support Intel Virtualization Technology.
Hardware Prefetcher
Use this turn on/off the MLC streamer prefetcher.
Adjacent Cache Line Prefetch
Use this to turn on/off prefetching of adjacent cache lines.