Acer AC100S Acer AC100 Service Guide - Page 102

POST code checkpoints list Bootblock initialization code checkpoint The following table describes the Award common tasks carried out by POST. An unique checkpoint number denotes each task. . Checkpoint Before D1 D1 D0 D2 D3 D4 D5 D6 D7 D8 D9 DA Description Early chipset initialization is done. Early super I/O initialization is done including RTC and keyboard controller. NMI is disabled. Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch CMOS. Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum. Disable CACHE before memory detection. Execute full memory sizing module. Verify that flat mode is enabled. If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled. Test base 512KB memory. Adjust policies and cache first 8MB. Set stack. Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information. Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash. The Runtime module is uncompressed into memory. CPUID information is stored in memory. Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM. Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section of document for more information. 96 Chapter 8