Acer AL1716 AL1716W Service Guide - Page 4

1. Product Specification (continued) ACER AL1716W 3 Go to cover page 1.3 Interface Connectors: 1.3.1 The AC inlet connector shall have an IEC/CEE22 type male power receptacle for connection to mains power. The power cord exact type to be supplied in the appropriate Option Kit, shall be black have length of 1.8+/- 0.05 meters. 1.3.2 Signal connectors and cable: The analog signal cable shall be black and 1800 mini-meters; at the end of the analog cable shall be a molded-over, shielded, triple row, blue color D subminiature, 15 positions connector. The CPU connection shall have captive screw locks, which will be adequate for hand tightening. The monitor connection may use small screws. 1.3.3 Connector pin assignment: D-SUB Pin Signal 1 Red-Video 2 Green-Video 3 Blue-Video 4 GND 5 Self Test Pin Signal 6 Red-GND 7 Green-GND 8 Blue-GND 9 + 5V 10 DDC-GND Pin Signal 11 GND 12 DDC-SDL 13 H-SYNC 14 V-SYNC 15 DDC-SCL Power Board Connector Pin Signal 1 GND 2 GND 3 GND 4 5.2V 5 5.2V 6 5.2V 7 5.2V 8 BKLT-EN 9 BKLT-ADJ Flat Panel Connector Terminal no. Symbol Function Note 1 GND Ground 2 VDD Power supply: +0.5V 3 VDD Power supply: +0.5V 4 NC Reserved for supplier test point 5 NC Reserved for supplier test point 6 NC Reserved for supplier test point 7 NC Reserved for supplier test point 8 Odd_Rin0- - LVDS differential data input (R0-R5, G0) (2) 9 Odd_Rin0+ + LVDS differential data input (R0-R5, G0) (2) 10 GND Ground 11 Odd_Rin1- - LVDS differential data input (G1-G5, B0-B1) (2) 12 Odd_Rin1+ + LVDS differential data input (G1-G5, B0-B1) (2) 13 GND Ground 14 Odd_Rin2- - LVDS differential data input (B2-B5, NC, NC, DE) (2) 15 Odd_Rin2+ + LVDS differential data input (B2-B5, NC, NC, DE) (2) 16 GND Ground 17 Odd_ClkIN- - LVDS differential clock input (2) 18 Odd_ClkIN+ + LVDS differential clock input (2) 19 GND Ground 20 Even_Rin0- - LVDS differential data input (R0-R5, G0) 21 Even_Rin0+ + LVDS differential data input (R0-R5, G0) 22 GND Ground 23 Even_Rin1- - LVDS differential data input (G1-G5, B0-B1) 24 Even_Rin1+ + LVDS differential data input (G1-G5, B0-B1) 25 GND Ground 26 Even_Rin2- - LVDS differential data input (B2-B5, NC, NC, DE) 27 Even_Rin2+ + LVDS differential data input (B2-B5, NC, NC, DE) 28 GND Ground 29 Even_ClkIN- - LVDS differential clock input 30 Even_ClkIN+ + LVDS differential clock input 1.4 Input Signals (Analog RGB Signal Input): No. Symbol Item 1 Fh Horizontal Frequency 2 Fv Vertical Frequency 3 Fclk Locked Pixel Clock Frequency 4 Vih Hi Level Input 5 Vil Low Level Input 6 Video RGB Analog Video Level Min Normal 31 56 2 0 0 Max 83 76 135 5 0.8 0.735 Unit Remark kHz Minimum range Hz Minimum range MHz V Note 1) V Note 1) V 75Ω to Ground Note 1: 2.2k to Ground, Schmitt-Triggers Input, Supported 3.3V device H & V sync. output. 1.4.1 Video Signal Amplitudes The three video inputs consist of Red, Green, and Blue signals, each with its own coaxial cable terminated at the monitor. These video signals are analog levels, where 0V corresponds to black, and 735 mV is the maximum signal amplitude for the respective color, when each signal is terminated by a nominal 75.0 ohm. For a given monitor luminance levels are measured using this defined video amplitude driving a monitor meeting the termination requirements. The signal amplitude is not to be readjusted to compensate for variations in termination impedance. 1.4.2 Video Signal Termination Impedance This analog video signal termination shall be 75 ohm +/- 2% which shall be resistive with a negligible reactive component. 1.4.3 Synchronization (Sync) Signals The Horizontal Sync (HS) TTL signal is used to initiate the display of a horizontal line. HS may be either active high or active low, depending upon the timing. The Vertical Sync (VS) TTL signal is used to initiate the display of a new frame. VS may be either active high or active low, depending on the timing. 1.4.4 Sync Signal Levels The monitor must accept sync signals from both 3.3V and 5V TTL logic families. The inputs shall sense a logic 0 when the input is 0.8V or less and shall sense a logic 1 when the input is 2.0V or greater. In addition to these level requirements, there shall also be a minimum of 0.3V hysteresis provided for noise immunity (typically by using a Schmitt Trigger input). That is, the input level at which the monitor actually detects a logic 0 shall be at least 0.3V lower than the level at which it actually detects a logic 1.