Acer Aspire ZS600 Acer Aspire ZS600 Desktop Service Guide - Page 201

Bootblock Recovery Code Checkpoints, Table 4-2.

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Table 4-2. Checkpoint D5 D6 D7 D8 D9 DA DC E1-E8 ECEE Description Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM. Copies compressed boot block code to memory in right segments. Copies BIOS from ROM to RAM for faster access. Performs main BIOS checksum and updates recovery status accordingly. Both key sequence and OEM specific method is checked to determine if BIOSrecovery is forced. Main BIOS checksum is tested. If BIOS recovery is necessary,control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints sectionfor more information. Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash. The Runtime module is uncompressed into memory. CPUID information is stored in memory. Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM. Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel).See POST Code Checkpoints section of document for more information. System is waking from ACPI S3 state. OEM memory detection/configuration error. This range is reserved for chipset vendors & system manufacturers. The error associated with this value may be different from one platform to the next. Bootblock Recovery Code Checkpoints 0 The Bootblock recovery code gets control when the BIOS determines that a BIOS recovery needs to occur because the user has forced the update or the BIOS checksum is corrupt. The following table describes the type of checkpoints that may occur during the Bootblock recovery portion of the BIOS. NOTE: NOTE: Checkpoints may differ between different platforms based on system configuration. Checkpoints may change due to vendor requirements, system chipset or option ROMs from add-in PCI devices Troubleshooting 4-7

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