Asus M5A78L LE User Manual - Page 54

Chipset

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Active CPU Cores [Auto] Allows you to manually turn ON/OFF a process core. Configuration options: [Auto] [Manual] 2nd / 3rd / 4th Core [On] These items only appear when you set Active CPU Cores to [Manual]. Configuration options: [On] [Off] Value (All Cores) [-2%] This item only appears when you set Advanced Clock Calibration to [All Cores]. It allows you to set the overclocking percentage for all the processor cores as a whole. Configuration options: [0%] [+2%] [+4%] [+6%] [+8%] [+10%] [+12%] [-2%] [-4%] [-6%] [-8%] [-10%] [-12%] Value (Core 0) / (Core 1) / (Core 2) / (Core 3) [-2%] These items only appear when you set Advanced Clock Calibration to [Per Core] and allow you to set the overclocking percentage for each process core separately. Configuration options: [0%] [+2%] [+4%] [+6%] [+8%] [+10%] [+12%] [-2%] [-4%] [-6%] [-8%] [-10%] [-12%] 2.4.3 Chipset NorthBridge Configuration DRAM Controller Configuration Bank Interleaving [Auto] Allows you to enable the bank memory interleaving. Configuration options: [Disabled] [Auto] Channel Interleaving [Auto] Allows you to enable the channel memory interleaving. Configuration options: [Disabled] [Address bits 6] [Address bits 12] [Auto] [XOR of Address bits [20:16, 6]] [XOR of Address bits [20:16, 9]] Enable Clock to All DIMMs [Disabled] Enables unused Clocks to DIMMs even though memory slots are not populated. Configuraiton options: [Enabled] [Disabled] MemClk Tristate C3/ATLVID [Disabled] Allows you to enable or disable MemClk Tri-Stating during C3 and Alt VID. Configuration options: [Disabled] [Enabled] Memory Hole Remapping [Enabled] Allows you to enable or disable memory remapping around memory hole. Configuration options: [Disabled] [Enabled] DCT Unganged Mode [Always] Allows you to select the unganged DRAM mode (64-bit width). Configuration options: [Auto] [Always] Power Down Enable [Disabled] Allows you to enable or disable DDR power down mode. Configuration options: [Disabled] [Enabled] 2-14 Chapter 2: BIOS information

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2-14
Chapter 2: BIOS information
2.4.3
Chipset
NorthBridge Configuration
DRAM Controller Configuration
Bank Interleaving [Auto]
Allows you to enable the bank memory interleaving. Configuration options: [Disabled] [Auto]
Channel Interleaving [Auto]
Allows you to enable the channel memory interleaving.
Configuration options: [Disabled] [Address bits 6] [Address bits 12] [Auto]
[XOR of Address bits [20:16, 6]] [XOR of Address bits [20:16, 9]]
Enable Clock to All DIMMs [Disabled]
Enables unused Clocks to DIMMs even though memory slots are not populated. Configuraiton
options: [Enabled] [Disabled]
MemClk Tristate C3/ATLVID [Disabled]
Allows you to enable or disable MemClk Tri-Stating during C3 and Alt VID.
Configuration options: [Disabled] [Enabled]
Memory Hole Remapping [Enabled]
Allows you to enable or disable memory remapping around memory hole.
Configuration options: [Disabled] [Enabled]
DCT Unganged Mode [Always]
Allows you to select the unganged DRAM mode (64-bit width).
Configuration options: [Auto] [Always]
Power Down Enable [Disabled]
Allows you to enable or disable DDR power down mode.
Configuration options: [Disabled] [Enabled]
Active CPU Cores [Auto]
Allows you to manually turn ON/OFF a process core. Configuration options: [Auto] [Manual]
2nd / 3rd / 4th Core [On]
These items only appear when you set
Active CPU Cores
to
[Manual]
.
Configuration options: [On] [Off]
Value (All Cores) [-2%]
This item only appears when you set
Advanced Clock Calibration
to
[All Cores]
. It
allows you to set the overclocking percentage for all the processor cores as a whole.
Configuration options: [0%] [+2%] [+4%] [+6%] [+8%] [+10%] [+12%] [-2%] [-4%]
[-6%] [-8%] [-10%] [-12%]
Value (Core 0) / (Core 1) / (Core 2) / (Core 3) [-2%]
These items only appear when you set
Advanced Clock Calibration
to
[Per Core]
and allow you to set the overclocking percentage for each process core separately.
Configuration options: [0%] [+2%] [+4%] [+6%] [+8%] [+10%] [+12%] [-2%] [-4%]
[-6%] [-8%] [-10%] [-12%]