Asus PR-DLS533 Manual PDF file for PR-DLS533 - Page 22
Core specifications
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1.4.2 Core specifications 1 DDR DIMM sockets. These six 184-pin DIMM sockets support up to 12GB system memory using registered ECC PC2100/1600 DDR DIMMs. 2 8-pin 12V SSI power connector. This power connector is for an ATX power supply. 3 24/20-pin ATX power connector. This power connector is for an ATX power supply. 4 ServerWorks® Grand Champion LE north bridge (CMIC-LE). The Champion Memory and I/O Controller LE (CMIC-LE) acts as the host bridge of the Grand Champion Low End (GCLE) SystemSet. The CMIC-LE device interfaces directly to the processor bus, and integrates the functions of the main memory controller and the Inter Module Bus (IMB) interface unit. The processor interface supports a 533/400MHz Front Side Bus (FSB) providing a 4.26GB/s or 3.2GB/s bandwidth, 2-way interleaved memory up to 12GB using registered ECC PC2100/1600 DDR DIMMs, and two high speed IMBs plus one thin IMB to connect to the south bridge CSB5. 5 DIP switches. This 5-switch Dual Inline Package (DIP) allows you to set the CPU external frequency. 6 603/604-pin CPU sockets. Two 603/604-pin surface mount, Zero Insertion Force (ZIF) sockets for the Intel® Xeon™ processor with 512KB L2 cache and a 533/400 MHz system bus that allows up to 4.26GB/s or 3.2GB/s data transfer rate. 7 IDE connectors. These dual-channel bus master IDE connectors support up to four Ultra DMA/100/66, PIO Modes 3 & 4 IDE devices. Both the primary (blue) and secondary (black) connectors are slotted to prevent incorrect insertion of the IDE ribbon cable. 8 ServerWorks® Champion south bridge (CSB5). The Champion South Bridge (CSB5) primarily acts as a PCI to Low Pin Count (LPC) bridge, but also supports several integrated functions including dual-channel ATA/100 IDE controller, 4-port USB 1.1 interface, ACPI power management and detection, XIO-APIC, and legacy functions 8237DMA, 8259APIC, and 8254 timer. 1-8 Chapter 1: Product introduction