Asus Pro H610M-C D4-CSM Intel 600 series Channel BIOS UM English - Page 23
DRAM WRITE to READ Delay L, DRAM REF Cycle Time Same Bank
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DRAM RAS# ACT Time Configuration options: [Auto] [1] - [511] DRAM Command Rate Configuration options: [Auto] [1N] [2N] [3N] [N:1] The following item appears only when DRAM Command Rate is set to [N:1]. N to 1 ratio Number of bubbles between each valid command cycle. Configurations: [1] - [7] Secondary Timings DRAM RAS# to RAS# Delay L Configuration options: [Auto] [1] - [63] DRAM RAS# to RAS# Delay S Configuration options: [Auto] [1] - [127] DRAM REF Cycle Time Configuration options: [Auto] [1] - [65535] DRAM REF Cycle Time 2 Configuration options: [Auto] [1] - [65535] DRAM REF Cycle Time Same Bank Configuration options: [Auto] [1] - [1023] DRAM Refresh Interval Configuration options: [Auto] [1] - [262143] DRAM WRITE Recovery Time Configuration options: [Auto] [1] - [234] DRAM READ to PRE Time Configuration options: [Auto] [1] - [255] DRAM FOUR ACT WIN Time Configuration options: [Auto] [1] - [511] DRAM WRITE to READ Delay Configuration options: [Auto] [1] - [15] DRAM WRITE to READ Delay L Configuration options: [Auto] [1] - [15] DRAM WRITE to READ Delay S Configuration options: [Auto] [1] - [15] DRAM CKE Minimum Pulse Width Configuration options: [Auto] [0] - [127] DRAM Write Latency Configuration options: [Auto] [1] - [255] PRIME / ProArt / TUF GAMING Intel 600 Series BIOS Manual 23
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