Biostar GF8200C M2 Bios Setup - Page 29

DRAM Timing Configuration

Page 29 highlights

GF8100 M2+ TE/GF8200C M2+ BIOSManual DRAM Timing Configuration BIOS SETU P U TILITY Performance DRAM Timing Co nfiguration Memory CLK CAS Latency( Tcl) RAS/CAS Dela y(Trcd) Row Precharg e Time(Trp) Min Active R AS(Tras) RAS/RAS Dela y(Trrd) Row Cycle (T rc) Command Rate (CR) > Memory Confi guration DRAM Timing Mo de CAS Latency( CL) 2T Command TRCD TRP tRTP [Aut o] [Aut o] [Aut o] [Aut o] [Aut o] [Aut o] S elect Screen S elect Item EnterG o to Sub Screen F1 G eneral Help F10 S ave and Exit ESC E xit vxx .xx (C)Copyright 1985-200x, American Me gatrends, Inc. Memory Configuration Memory Configu ration Bank Interleav ing Enable Clock t o All DIMMs MemClk Tristat e C3/ATLVID Memory Hole Re mapping Power Down Ena ble Power Down M ode BIOS SETU P U TILITY Performance [Aut o] [Dis abled] [Dis abled] [Ena bled] [Dis abled] [Cha nnel] Enable Bank Memory Interleaving S elect Screen S elect Item +- C hange Option F1 G eneral Help F10 S ave and Exit ESC E xit vxx .xx (C)Copyright 1985-200x, American Me gatrends, Inc. Bank Interleaving Bank Interleaving is an advanced chipset technique used to improve memory perform ance. Memory interleaving increases bandwidth by allowing simultaneous access to more than one piece ofmemory. Options: Auto (Default) / Disabled 28

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GF8100 M2+ TE/GF8200C M2+ BIOS Manual
28
DRAM Timing Configuration
BIOS SETUP UTILITY
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Go to Sub Screen
General Help
Save and Exit
Exit
Enter
F1
F10
ESC
DRAM Timing Configuration
Memory CLK
CAS Latency(Tcl)
RAS/CAS Delay(Trcd)
Row Precharge Time(Trp)
Min Active RAS(Tras)
RAS/RAS Delay(Trrd)
Row Cycle (Trc)
Command Rate(CR)
> Memory Configuration
DRAM Timing Mode
[Auto]
CAS Latency(CL)
[Auto]
2T Command
[Auto]
TRCD
[Auto]
TRP
[Auto]
tRTP
[Auto]
Performance
Memory Configuration
BIOS SETUP UTILITY
vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc.
Select Screen
Select Item
Change Option
General Help
Save and Exit
Exit
+-
F1
F10
ESC
Memory Configuration
Bank Interleaving
[Auto]
Enable Clock to All DIMMs
[Disabled]
MemClk Tristate C3/ATLVID
[Disabled]
Memory Hole Remapping
[Enabled]
Power Down Enable
[Disabled]
Power Down Mode
[Channel]
Enable Bank Memory
Interleaving
Performance
Bank Interleaving
Bank Interleaving is an advanced chipset technique used to improve memory
performance. Memory interleaving increases bandwidth by allowing simultaneous
access to more than one piece of memory.
Options:
Auto (Default) / Disabled