Biostar P4M890-M7 TE Bios Setup - Page 20
Memory Hole, System BIOS Cacheable, Top Performance
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P4M900-M7 SE/P4M890-M7 TE PCI Delay Transaction The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles. Select Enabled to support compliance with PCI specification. The Choices: Enabled (default), Disabled. VLink mode selection This item allows you to select Vlink mode. The Choices: By Auto (default), Mode 0 , Mode 1, Mode 2, Mode 3, Mode 4. VLink 8X Support This item allows you to enable or disable VLink 8X support. The Choices: Enabled (default), Disabled. VIA PWR Management The Choices: Enabled (default), Disabled. Memory Hole You can reserve this area of system memory for ISA adapter ROM. When this area is reserved it cannot be cached. Check the user information of peripherals that need to use this area of system memory for the memory requirements. The Choices: Disabled (default), 15M-16M. System BIOS Cacheable Selecting the "Enabled" option allows caching of the system BIOS ROM at F0000h-FFFFFh, which is able to improve the system performance. However, any programs that attempts to write to this memory block will cause conflicts and result in system errors. The Choices: Enabled (default), Disabled. Top Performance The Choices: Disabled (default), Enabled. 19