Biostar P4VMA-M P4VMA-M BIOS setup guide - Page 14

Advanced Chipset Features - via chipset

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4 Advanced Chipset Features This submenu allows you to configure the specific features of the chipset installed on your system. This chipset manage bus speeds and access to system memory resources, such as DRAM. It also coordinates communications with the PCI bus. The default settings that came with your system have been optimized and therefore should not be changed unless you are suspicious that the settings have been changed incorrectly. Figure 4. Advanced Chipset Setup DRAM Clock/Drive Control To control the Clock. If you highlight the literal "Press Enter" next to the "DRAM Clock" label and then press the enter key, it will take you a submenu with the following options: DRAM Clock This item determines DRAM clock following 100MHz, 133MHz or By SPD. The Choices: 100MHz, 133MHz, By SPD (default). DRAM Timing This item determines DRAM clock/ timing follow SPD or not. The Choices: By SPD(default), Manual. SDRAM CAS Latency When DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. 13

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4 Advanced Chipset Features
This submenu allows you to configure the specific features of the chipset installed on your
system. This chipset manage bus speeds and access to system memory resources, such as
DRAM. It also coordinates communications with the PCI bus. The default settings that came
with your system have been optimized and therefore should not be changed unless you are
suspicious that the settings have been changed incorrectly.
±
Figure 4. Advanced Chipset Setup
DRAM Clock/Drive Control
To control the Clock. If you highlight the literal “Press Enter” next to the “DRAM Clock”
label and then press the enter key, it will take you a submenu with the following options:
DRAM Clock
This item determines DRAM clock following 100MHz, 133MHz or By SPD.
The Choices:
100MHz, 133MHz,
By SPD
(default).
DRAM Timing
This item determines DRAM clock/ timing follow SPD or not.
The Choices: By
SPD
(default), Manual.
SDRAM CAS Latency
When DRAM is installed, the number of clock cycles of CAS latency depends on
the DRAM timing.
13