Biostar P4VMA-M P4VMA-M BIOS setup guide - Page 16

CPU & PCI Bus Control - 2 3 manual

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By choosing "Auto" the system BIOS will the AGP output Buffer Drive strength P Ctrl by AGP Card. By choosing "Manual", it allows user to set AGP output Buffer Drive strength P Ctrl by manual. The Choices: Auto (default), Manual. AGP Driving Value While AGP driving control item set to "Manual", it allows user to set AGP driving. The Choices: DA (default). AGP Fast Write The Choices: Enabled, Disabled (default). AGP Master 1 WS Write When Enabled, writes to the AGP (Accelerated Graphics Port) are executed with one wait states. The Choices: Disabled (default), Enabled. AGP Master 1 WS Read When Enabled, read to the AGP (Accelerated Graphics Port) are executed with one wait states. The Choices: Disabled (default), Enabled. AGP 3.0 Calibration cycle The Choices: Disabled (default), Enabled. AGP Share Memory Size The Choices: 64M (default), Disabled. CPU & PCI Bus Control If you highlight the literal "Press Enter" next to the "CPU & PCI Bus Control" label and then press the enter key, it will take you a submenu with the following options: CPU to PCI Write Buffer When enabled, up to four Dwords of data. Can be written to the PCI bus without interrupting the CPU. When disabled, a write buffer is not used and the CPU read cycle will not be completed until the PCI bus signals that it is ready to receive the data. The Choices: Enabled (default), Disabled. PCI Master 0 WS Write When Enabled, writes to the PCI bus are executed with zero-wait states. The Choices: Enabled (default), Disabled. PCI Delay Transaction The chipset has an embedded 32-bit posted write buffer to support delay 15

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By choosing “Auto” the system BIOS will the AGP output Buffer Drive strength
P Ctrl by AGP Card. By choosing “Manual”, it allows user to set AGP output
Buffer Drive strength P Ctrl by manual.
The Choices: Auto
(default), Manual.
AGP Driving Value
While AGP driving control item set to “Manual”, it allows user to set AGP
driving.
The Choices: DA
(default).
AGP Fast Write
The Choices:
Enabled,
Disabled
(default).
AGP Master 1 WS Write
When Enabled, writes to the AGP (Accelerated Graphics Port) are executed with
one wait states.
The Choices: Disabled
(default), Enabled.
AGP Master 1 WS Read
When Enabled, read to the AGP (Accelerated Graphics Port) are executed with
one wait states.
The Choices: Disabled
(default), Enabled.
AGP 3.0 Calibration cycle
The Choices: Disabled
(default), Enabled.
AGP Share Memory Size
The Choices: 64M
(default), Disabled.
CPU & PCI Bus Control
If you highlight the literal “Press Enter” next to the “CPU & PCI Bus Control” label and
then press the enter key, it will take you a submenu with the following options:
CPU to PCI Write Buffer
When enabled, up to four Dwords of data. Can be written to the PCI bus without
interrupting the CPU. When disabled, a write buffer is not used and the CPU
read cycle will not be completed until the PCI bus signals that it is ready to
receive the data.
The Choices: Enabled
(default), Disabled.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero-wait states.
The Choices: Enabled
(default), Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
15