Compaq 307560-001 Novell GroupWise Performance Management on Compaq Servers - Page 10

System Processor CPU

Page 10 highlights

ECG007.0897 WHITE PAPER (cont.) 1...0 The subsystems to be discussed are: • CPU • Memory • Disk • Bus Architecture (Bridge vs. Dual PCI) • Networking System Processor (CPU) In contrast to a resource-sharing (file server) environment, a faster processor for an implementation of GroupWise on an IntranetWare Server yields faster client response times. In a resource-sharing environment, the system processor plays a less important role in performance tuning than the memory, disk, and network interface card. For Novell GroupWise, however, the processor is the most important subsystem for high performance. In the testing performed by the Novell and Compaq team, the performance of the Pentium processors was compared to that of the Pentium Pro processors. The type of processor and its associated architecture features have as much impact on performance as processor-rated clock speed. For example, the Pentium Pro processor offers outstanding performance that is partially attributed to the incorporation of the following dynamic execution features. • A superscalar architecture gives the processor the ability to execute multiple instructions per clock cycle. • Internal register renaming supports the execution of concurrent instructions. • Speculative execution of branches is supported via the processor's branch target buffer, which means the processor is able to predict the correct branch in most instances, thus increasing the number of instructions that can be executed out of order. • The processor fetches and decodes numerous instructions, which are then sent to an instruction pool that schedules instructions that have no dependencies on prior instructions to be executed even if the instruction is out of order. • Processor cache also has effect on performance. L1 cache(cache memory in the CPU it self) stores the most recent data and program instructions and provides this information to the server at the highest possible speeds. The systems L2 cache(near the CPU) has a 133 megahertz path to the CPU. L2 cache stores additional data and instructions. These two caches allow the CPU to function at higher rates of speed. Information that is not stored in either L1 or L2 caches must come from the main system memory at a speed of 66 megahertz, in turn slowing down the CPU. In other words, the larger the L2 cache is, the better performance will be.

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23

W
HITE
P
APER
(cont.)
10
ECG007.0897
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
.
The subsystems to be discussed are:
CPU
Memory
Disk
Bus Architecture (Bridge vs. Dual PCI)
Networking
System Processor (CPU)
In contrast to a resource-sharing (file server) environment, a faster processor for an
implementation of GroupWise on an IntranetWare Server yields faster client response times. In a
resource-sharing environment, the system processor plays a less important role in performance
tuning than the memory, disk, and network interface card. For Novell GroupWise, however, the
processor is the most important subsystem for high performance.
In the testing performed by the Novell and Compaq team, the performance of the Pentium
processors was compared to that of the Pentium Pro
processors. The type of processor and its
associated architecture features have as much impact on performance as processor-rated clock
speed. For example, the Pentium Pro processor offers outstanding performance that is partially
attributed to the incorporation of the following dynamic execution features.
A superscalar architecture gives the processor the ability to execute
multiple instructions per clock cycle.
Internal register renaming supports the execution of concurrent
instructions.
Speculative execution of branches is supported via the processor’s
branch target buffer, which means the processor is able to predict
the correct branch in most instances, thus increasing the number
of instructions that can be executed out of order.
The processor fetches and decodes numerous instructions, which
are then sent to an instruction pool that schedules instructions that
have no dependencies on prior instructions to be executed even if
the instruction is out of order.
Processor cache also has effect on performance. L1 cache(cache
memory in the CPU it self) stores the most recent data and
program instructions and provides this information to the server at
the highest possible speeds. The systems L2 cache(near the CPU)
has a 133 megahertz path to the CPU. L2 cache stores additional
data and instructions. These two caches allow the CPU to function
at higher rates of speed.
Information that is not stored in either L1 or L2 caches must come
from the main system memory at a speed of 66 megahertz, in turn
slowing down the CPU. In other words, the larger the L2 cache is,
the better performance will be.