EVGA 132-CK-NF79-A1 User Manual - Page 94

W to W Timing, CAS Latency, Clock Drive Strength, Command Per Clock, Async Latency

Get EVGA 132-CK-NF79-A1 PDF manuals and user guides View all EVGA 132-CK-NF79-A1 manuals
Add to My Manuals
Save this manual to your list of manuals

Page 94 highlights

Using NVIDIA Software lower cycle time results in better performance but is can instability. Adjustable from 0 to 6 cycles. ‰ W to W Timing The Write-to-Write (tWRWR) timing is the number of clock cycles between the last write and the subsequent Write command to the same physical bank. Adjustable from 2 to 15 cycles. ‰ CAS Latency The CAS Latency (tCL) is the time (in number of clock cycles) that elapses after the memory controller sends a request to read a memory location and before the data is sent to the module's output pins. The value shown cannot be changed. ‰ Clock Drive Strength This value is filled in by the system and can not be changed by the user. ‰ Command Per Clock The Command Per Clock (tCPC) sets the Command Rate for the memory controller. The value shown cannot be changed ‰ Async Latency This value is filled in by the system and can not be changed by the user. EVGA Corporation January 11, 2008 | DU-03751-001_v01 83

  • 1
  • 2
  • 3
  • 4
  • 5
  • 6
  • 7
  • 8
  • 9
  • 10
  • 11
  • 12
  • 13
  • 14
  • 15
  • 16
  • 17
  • 18
  • 19
  • 20
  • 21
  • 22
  • 23
  • 24
  • 25
  • 26
  • 27
  • 28
  • 29
  • 30
  • 31
  • 32
  • 33
  • 34
  • 35
  • 36
  • 37
  • 38
  • 39
  • 40
  • 41
  • 42
  • 43
  • 44
  • 45
  • 46
  • 47
  • 48
  • 49
  • 50
  • 51
  • 52
  • 53
  • 54
  • 55
  • 56
  • 57
  • 58
  • 59
  • 60
  • 61
  • 62
  • 63
  • 64
  • 65
  • 66
  • 67
  • 68
  • 69
  • 70
  • 71
  • 72
  • 73
  • 74
  • 75
  • 76
  • 77
  • 78
  • 79
  • 80
  • 81
  • 82
  • 83
  • 84
  • 85
  • 86
  • 87
  • 88
  • 89
  • 90
  • 91
  • 92
  • 93
  • 94
  • 95
  • 96
  • 97
  • 98
  • 99
  • 100
  • 101
  • 102
  • 103
  • 104
  • 105
  • 106
  • 107
  • 108
  • 109
  • 110
  • 111
  • 112
  • 113
  • 114
  • 115
  • 116
  • 117
  • 118
  • 119
  • 120
  • 121
  • 122
  • 123
  • 124
  • 125
  • 126
  • 127
Using NVIDIA Software
EVGA Corporation
January 11, 2008
|
DU-03751-001_v01
83
lower cycle time results in better performance but is can instability.
Adjustable from 0 to 6 cycles.
W to W Timing
The Write-to-Write (tWRWR) timing is the number of clock cycles
between the last write and the subsequent Write command to the same
physical bank. Adjustable from 2 to 15 cycles.
CAS Latency
The CAS Latency (tCL) is the time (in number of clock cycles) that
elapses after the memory controller sends a request to read a memory
location and before the data is sent to the module's output pins. The
value shown cannot be changed.
Clock Drive Strength
This value is filled in by the system and can not be changed by the user.
Command Per Clock
The Command Per Clock (tCPC) sets the Command Rate for the
memory controller. The value shown cannot be changed
Async Latency
This value is filled in by the system and can not be changed by the user.