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Fujitsu MH2060AH Manual/User Guide - Page 106

Bit 15-14: Reserved, The Identify information - mht2060ah specs

UPC - 810884006940

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Interface Bit 14-8: Undefined Bit 7: Removable disk drive = 1 Bit 6: Fixed drive = 1 Bit 5-3: Undefined Bit 2: IDENTIFY DEVICE Valid = 0 Bit 1-0: Reserved *2 Word 1, 3, 6, 60-61 Word 01 Word 03 Word 06 Word 60-61 MHT2080AH X'3FFF' X'10' X'3F' X'950F8B0' MHT2060AH X'3FFF' X'10' X'3F' X'6FC7C80' MHT2040AH X'3FFF' X'10' X'3F' X'4A85300' *3 Status of the Word 2 Identify information is shown as follows: 37C8h The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete. 738Ch The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete. 8C73h The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete. C837h The device requires the SET FEATURES sub-command after the power-on sequence in order to spin-up. The Identify information is incomplete. Others Reserved *4 Word 49: Capabilities Bit 15-14: Reserved Bit 13: Standby timer value. ATA spec is '1.' Bit 12: Reserved Bit 11: 1 = Supported Bit 10: 0 = Disable inhibition Bit 7-0: Undefined Bit 8: 1 = LBA Supported Bit 9: 1 = DMA Supported 5-36 C141-E195-02EN

Section	Page
Front Cover	1
FOR SAFE OPERATION	2
Revision History	3
Preface	5
Important Alert Items	9
Manual Organization	11
Contents	13
Illustrations	18
Figures	18
Tables	20
CHAPTER 1 Device Overview	21
1.1 Features	22
1.1.1 Functions and performance	22
1.1.2 Adaptability	22
1.1.3 Interface	23
1.2 Device Specifications	24
1.2.1 Specifications summary	24
1.3 Power Requirements	25
1.4 Environmental Specifications	28
1.5 Acoustic Noise	29
1.6 Shock and Vibration	29
1.7 Reliability	30
1.8 Error Rate	31
1.9 Media Defects	31
1.10 Load/Unload Function	31
1.11 Advanced Power Management	32
CHAPTER 2 Device Configuration	35
2.1 Device Configuration	36
2.2 System Configuration	37
2.2.1 ATA interface	37
2.2.2 1 drive connection	37
2.2.3 2 drives connection	38
CHAPTER 3 Installation Conditions	39
3.1 Dimensions	40
3.2 Mounting	41
3.3 Cable Connections	47
3.3.1 Device connector	47
3.3.2 Cable connector specifications	48
3.3.3 Device connection	48
3.3.4 Power supply connector (CN1)	48
3.4 Jumper Settings	49
3.4.1 Location of setting jumpers	49
3.4.2 Factory default setting	50
3.4.3 Master drive-slave drive setting	50
3.4.4 CSEL setting	51
3.4.5 Power Up in Standby setting	52
CHAPTER 4 Theory of Device Operation	53
4.1 Outline	54
4.2 Subassemblies	54
4.2.1 Disk	54
4.2.2 Spindle	54
4.2.3 Actuator	54
4.2.4 Air filter	55
4.3 Circuit Configuration	55
4.4 Power-on Sequence	58
4.5 Self-calibration	59
4.5.1 Self-calibration contents	59
4.5.2 Execution timing of self-calibration	60
4.5.3 Command processing during self-calibration	60
4.6 Read/write Circuit	61
4.6.1 Read/write preamplifier (PreAMP)	61
4.6.2 Write circuit	61
4.6.3 Read circuit	62
4.6.4 Digital PLL circuit	63
4.7 Servo Control	64
4.7.1 Servo control circuit	64
4.7.2 Data-surface servo format	66
4.7.3 Servo frame format	68
4.7.4 Actuator motor control	69
4.7.5 Spindle motor control	70
CHAPTER 5 Interface	71
5.1 Physical Interface	72
5.1.1 Interface signals	72
5.1.2 Signal assignment on the connector	73
5.2 Logical Interface	76
5.2.1 I/O registers	77
5.2.2 Command block registers	78
5.2.3 Control block registers	83
5.3 Host Commands	84
5.3.1 Command code and parameters	84
5.3.2 Command descriptions	88
5.4 Command Protocol	179
5.4.1 PIO Data transferring commands from device to host	179
5.4.2 PIO Data transferring commands from host to device	182
5.4.3 Commands without data transfer	184
5.4.4 Other commands	185
5.4.5 DMA data transfer commands	185
5.5 Ultra DMA Feature Set	188
5.5.1 Overview	188
5.5.2 Phases of operation	189
5.5.3 Ultra DMA data in commands	189
5.5.4 Ultra DMA data out commands	194
5.5.5 Ultra DMA CRC rules	198
5.5.6 Series termination required for Ultra DMA	199
5.6 Timing	200
5.6.1 PIO data transfer	200
5.6.2 Multiword data transfer	201
5.6.3 Ultra DMA data transfer	202
5.6.4 Power-on and reset	215
CHAPTER 6 Operations	217
6.1 Device Response to the Reset	218
6.1.1 Response to power-on	218
6.1.2 Response to hardware reset	219
6.1.3 Response to software reset	221
6.1.4 Response to diagnostic command	222
6.2 Power Save	223
6.2.1 Power save mode	223
6.2.2 Power commands	225
6.3 Defect Processing	225
6.3.1 Spare area	225
6.3.2 Alternating processing for defective sectors	226
6.4 Read-ahead Cache	228
6.4.1 DATA buffer structure	228
6.4.2 Caching operation	229
6.4.3 Using the read segment buffer	231
6.5 Write Cache	235
6.5.1 Cache operation	235
Glossary	237
Acronyms and Abbreviations	241
Index	243
Comment Form	245