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Fujitsu MHG2102AT Manual/User Guide - Page 34

MHG2102AT, MHH2064AT, MHH2032AT, MHH2048AT

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2.1 Device Configuration Head 5 4 3 2 1 0 MHG2102AT Head 3 2 1 0 MHH2064AT 2 1 0 MHH2048AT Head 1 0 MHH2032AT Figure 2.2 Configuration of disk media heads (3) Spindle motor The disks are rotated by a direct drive Hall-less DC motor. (4) Actuator The actuator uses a revolving voice coil motor (VCM) structure which consumes low power and generates very little heat. The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read/write head. If the power is not on or if the spindle motor is stopped, the head assembly stays in the specific CSS zone on the disk and is fixed by a mechanical lock. (5) Air circulation system The disk enclosure (DE) is sealed to prevent dust and dirt from entering. The disk enclosure features a closed loop air circulation system that relies on the blower effect of the rotating disk. This system continuously circulates the air through the circulation filter to maintain the cleanliness of the air within the disk enclosure. (6) Read/write circuit The read/write circuit uses a LSI chip for the read/write preamplifier. It improves data reliability by preventing errors caused by external noise. (7) Controller circuit The controller circuit consists of an LSI chip to improve reliability. The highspeed microprocessor unit (MPU) achieves a high-performance AT controller. C141-E070-02EN 2-3

Section	Page
Front title	1
Preface	6
Contents	14
Illustrations	19
Tables	20
CHAPTER 1 Device Overview	22
1.1 Features	23
1.1.1 Functions and performance	23
1.1.2 Adaptability	23
1.1.3 Interface	24
1.2 Device Specifications	25
1.2.1 Specifications summary	25
1.2.2 Model and product number	26
1.3 Power Requirements	26
1.4 Environmental Specifications	28
1.5 Acoustic Noise	29
1.6 Shock and Vibration	29
1.7 Reliability	30
1.8 Error Rate	31
1.9 Media Defects	31
CHAPTER 2 Device Configuration	32
2.1 Device Configuration	33
2.2 System Configuration	35
2.2.1 ATA interface	35
2.2.2 1 drive connection	35
2.2.3 2 drives connection	35
CHAPTER 3 Installation Conditions	38
3.1 Dimensions	39
3.2 Mounting	41
3.3 Cable Connections	46
3.3.1 Device connector	46
3.3.2 Cable connector specifications	47
3.3.3 Device connection	47
3.3.4 Power supply connector (CN1)	48
3.4 Jumper Settings	48
3.4.1 Location of setting jumpers	48
3.4.2 Factory default setting	49
3.4.3 Master drive-slave drive setting	49
3.4.4 CSEL setting	50
CHAPTER 4 Theory of Device Operation	52
4.1 Outline	53
4.2 Subassemblies	53
4.2.1 Disk	53
4.2.2 Head	53
4.2.3 Spindle	54
4.2.4 Actuator	54
4.2.5 Air filter	54
4.3 Circuit Configuration	55
4.4 Power-on Sequence	57
4.5 Self-calibration	58
4.5.1 Self-calibration contents	58
4.5.2 Execution timing of self-calibration	59
4.5.3 Command processing during self-calibration	60
4.6 Read/write Circuit	60
4.6.1 Read/write preamplifier (PreAMP)	60
4.6.2 Write circuit	61
4.6.3 Read circuit	63
4.6.4 Digital PLL circuit	64
4.7 Servo Control	65
4.7.1 Servo control circuit	65
4.7.2 Data-surface servo format	69
4.7.3 Servo frame format	69
4.7.4 Actuator motor control	70
4.7.5 Spindle motor control	71
CHAPTER 5 Interface	74
5.1 Physical Interface	75
5.1.1 Interface signals	75
5.1.2 Signal assignment on the connector	76
5.2 Logical Interface	79
5.2.1 I/O registers	80
5.2.2 Command block registers	81
5.2.3 Control block registers	86
5.3 Host Commands	86
5.3.1 Command code and parameters	87
5.3.2 Command descriptions	89
5.3.3 Error posting	144
5.4 Command Protocol	146
5.4.1 Data transferring commands from device to host	146
5.4.2 Data transferring commands from host to device	148
5.4.3 Commands without data transfer	150
5.5 Ultra DMA Feature Set	153
5.5.1 Overview	153
5.5.2 Phases of operation	154
5.5.2.1 Ultra DMA burst initiation phase	154
5.5.2.2 Data transfer phase	155
5.5.3 Ultra DMA data in commands	156
5.5.3.1 Initiating an Ultra DMA data in burst	156
5.5.3.2 The data in transfer	157
5.5.3.3 Pausing an Ultra DMA data in burst	157
5.5.3.4 Terminating an Ultra DMA data in burst	158
5.5.4 Ultra DMA data out commands	161
5.5.4.1 Initiating an Ultra DMA data out burst	161
5.5.4.2 The data out transfer	161
5.5.4.3 Pausing an Ultra DMA data out burst	162
5.5.4.4 Terminating an Ultra DMA data out burst	163
5.5.5 Ultra DMA CRC rules	165
5.5.6 Series termination required for Ultra DMA	167
5.6 Timing	168
5.6.1 PIO data transfer	168
5.6.2 Single word DMA data transfer	170
5.6.3 Multiword DMA data transfer	171
5.6.4 Transfer of Ultra DMA data	172
5.6.4.1 Starting of Ultra DMA data In Burst	172
5.6.4.2 Ultra DMA data burst timing requirements	173
5.6.4.3 Sustained Ultra DMA data in burst	175
5.6.4.4 Host pausing an Ultra DMA data in burst	176
5.6.4.5 Device terminating an Ultra DMA data in burst	177
5.6.4.6 Host terminating an Ultra DMA data in burst	178
5.6.4.7 Initiating an Ultra DMA data out burst	179
5.6.4.8 Sustained Ultra DMA data out burst	180
5.6.4.9 Device pausing an Ultra DMA data out burst	181
5.6.4.10 Host terminating an Ultra DMA data out burst	182
5.6.4.11 Device terminating an Ultra DMA data in burst	183
5.6.5 Power-on and reset	184
CHAPTER 6 Operations	186
6.1 Device Response to the Reset	187
6.1.1 Response to power-on	187
6.1.2 Response to hardware reset	189
6.1.3 Response to software reset	190
6.1.4 Response to diagnostic command	191
6.2 Address Translation	192
6.2.1 Default parameters	192
6.2.2 Logical address	193
6.3 Power Save	194
6.3.1 Power save mode	194
6.3.2 Power commands	196
6.4 Defect Management	196
6.4.1 Spare area	197
6.4.2 Alternating defective sectors	197
6.5 Read-Ahead Cache	199
6.5.1 Data buffer configuration	199
6.5.2 Caching operation	199
6.5.3 Usage of read segment	201
6.5.3.1 Mis-hit (no hit)	201
6.5.3.2 Sequential read	202
6.5.3.3 Full hit (hit all)	205
6.5.3.4 Partially hit	206
6.6 Write Cache	207
Glossary	210
Acronyms and Abbreviations	214
Index	216
Comment Form	221
spine	222