HP LH4r Architecture/Technology Overview - Page 4

ZKLWHýSDSHU +3ý 1HW6HUYHUý /;Uýåèíí bridge, combined with the Profusion chipset, permits the system to handle long bursts of data (streaming) due to the write-posting buffers, another feature that improves data flow and further balances the system. The paper continues by providing detailed information on the following points: • The Profusion design supports from two to eight Intel Pentium II or Pentium III Xeon processors. • The memory design facilitates two subsystems of dual interleaved ECC memory with up to 16 DIMMs in each memory bank. • The standard configuration for the LXr 8500 includes two cache coherency filters for improved server performance. • The I/O port connects to four Bus-to-PCI bridges that together support ten hot-plug, 64-bit PCI slots; four of these are 66 MHz PCI slots and the remaining six are 33 MHz PCI slots. Processors The HP NetServer LXr 8500 uses Pentium III Xeon processors at 550 MHz. The server supports from one to eight of these processors. The Intel Pentium III Xeon processor includes the latest improvements in performance-enabling instruction sets, although it still provides the same cartridge form factor as its predecessor, the Pentium II Xeon. The Pentium III Xeon processors will be available with L2 cache sizes of 1MB and 2MB. Larger Level 2 caches serve to reduce system bus activity enhancing performance, especially in systems with over four processors. The NetServer LXr 8500 will be able to be upgraded to future generations of Pentium III Xeon processors. Memory The Profusion chip set supports up to 32 GB of synchronous dynamic random-access memory (SDRAM), ideal for memory-intensive applications such as enterprise resource planning and messaging. The system divides the memory into two carrier boards of up to 16 GB of interleaved SDRAM, that are connected to two ports on the Profusion system controller switch. Interleaving improves memory access performance because both memory buses can be simultaneously active. One bus responds to odd-numbered cache line requests, the other to the even-numbered lines. Two buses increase memory bandwidth, reduce access conflicts and increase the maximum memory supported. (Memory interleaving is only available when both memory carrier boards are included in the system configuration.) 4