HP ML150 HP ProLiant Intel-based 100-series G6 server technology - Page 10

Memory Mirroring with DDR-3 ProLiant 100-series G6 servers using the Xeon 5500 processor support memory mirroring which protects the system against uncorrectable memory errors that would otherwise result in a system hang or crash. Mirroring occurs when all data is written to both sets of physical memory in channels one and two. Administrators can configure memory mirroring through BSU. To implement mirroring with DDR-3, the two memory channels must be populated identically. The third memory channel must be empty. If an uncorrectable error occurs, the system automatically directs the read to the mirrored location to obtain the correct data. The OS does not revert to Advanced ECC Mode until the DIMM is replaced and the server rebooted. Since each mirrored DIMM is one of a pair, one DIMM can be protected by mirroring while another is degraded. As a result, even after mirroring is degraded by a DIMM failure, the other DIMM in the mirrored pair is still protected by Advanced ECC. Memory channel interleaving Xeon 3400 and 5500 Series processors retrieve data from the memory DIMMs in 64-byte chunks. With channel interleaving, the system is set up so that each consecutive 64-byte chunk in the memory map is physically transferred by means of alternate routing through the three available data channels. The result is that when the memory controller needs to access a block of logically contiguous memory, the requests are distributed more evenly across the three channels rather than potentially stacking up in the request queue of a single channel. This alternate routing decreases memory access latency and increases performance. However, interleaving memory channels increases the probability that more DIMMs need to be kept in an active state (requiring more power) since the memory controller alternates between channels and between DIMMs. This is discussed further in the "Power and thermal technologies" section. Lockstep memory mode Lock-step mode is an advanced memory protection feature supported in ProLiant Intel 100-series G6 servers using the Xeon 5500 Series processor. It uses two of the Xeon 5500 processor's three memory channels to provide an even higher level of protection than Advanced ECC. In lockstep mode, two channels operate as a single channel-each write and read operation moves a data word two channels wide. The cache line is split across both channels to provide 2x 8-bit error detection and 8bit error correction within a single DRAM. In three-channel memory systems, the third channel is unused and left unpopulated. The Lockstep Memory mode is the most reliable memory protection method, but it reduces the total system memory capacity by a third in most systems. Performance is measurably slower than normal Advanced ECC mode, and uncorrectable memory errors can only be isolated to a pair of DIMMs instead of a single DIMM. Lock-Step mode is not the default operation; it must be enabled in BSU. For additional information about DDR-3 memory, see the technology brief titled "Memory technology evolution: an overview of system memory technologies" at http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf. 10