Home » HP Manuals » Servers » HP ProLiant DL360e » Manual Viewer

HP ProLiant DL360e Configuring and using DDR3 memory with HP ProLiant Gen8 Ser - Page 24

Setting Memory Interleave, Setting Node Interleaving

Add to My Manuals
Save this manual to your list of manuals

Page 24 highlights

Setting Memory Interleave Diasabling Memory Interleaving This option is available from the Advanced Power Management menu in RBSU. Disabling memory interleaving saves some power per DIMM, but incurs a performance penalty. Setting Node Interleaving This option is available from the RBSU Advanced Options menu. Enabling Node Interleaving disables the NUMA architecture properties of the system. In NUMA configuration, each CPU core allocates memory closest to it. If all this near memory is consumed, then it will allocate memory attached to the remote CPU socket. When node interleaving is enabled, BIOS builds the system memory map by first using all memory attached to the first processor and then all memory from the second processor. When Node Interleaving is enabled, memory addresses are interleaved across the memory installed on each processor, and each CPU core allocates memory equally from both processor sockets. Some workloads that use shared data sets may see improved performance with this feature enabled. Figure 15: ROM-Based Setup Utility, Node Interleaving setting 24

Section	Page
Introduction	3
Overview of DDR3 memory technology	3
Basics of DDR3 memory technology	3
DDR3 Memory Technology	3
DDR3 Speeds	3
Basics of DIMMs	4
DRAM technology	4
Ranks	4
Speed	4
DDR3 DIMM types	5
Unbuffered DIMMs	5
Registered DIMMs	5
Load Reduced DIMMs	5
HP SmartMemory	6
HP Advanced Memory Error Detection	6
ProLiant Gen8 memory architecture and DDR3 Memory	7
ProLiant Gen8 memory Architecture	7
HP ProLiant Gen8 Servers	8
HP ProLiant Gen8 Processors	8
DDR3 memory for HP ProLiant Gen8 servers	9
Populating memory in HP ProLiant Gen8 servers	10
HP ProLiant Gen8 memory slot configurations	10
Population rules for HP ProLiant Gen8 servers	10
Rules for populating processors and DIMM slots	10
Rules for DIMM types	10
General rules	11
DIMM Population Order	11
Memory system operating speeds	12
Mixing DIMM speeds and DIMMs/channel	13
General population guidelines	13
Optimizing memory configurations	13
Optimizing for capacity	13
Optimizing for performance	14
Factors influencing latency	14
Factors influencing memory throughput	15
Number of memory channels and throughput	15
Memory speed and throughput	16
Number of DIMMs per channel and throughput	17
Mixing DIMM sizes	19
General guidelines	19
Optimizing for lowest power consumption	19
DIMM types and power consumption	19
Memory speed and power consumption	20
General guidelines when optimizing for power consumption	21
Optimizing for Resiliency	21
Understanding unbalanced memory configurations	22
0TMemory configurations that are unbalanced across channels	22
0TMemory configurations that are unbalanced across Processors	22
BIOS Settings for memory	23
Controlling Memory Speed	23
Setting Maximum Memory Bus Frequency	23
Setting Memory Interleave	24
Diasabling Memory Interleaving	24
Setting Node Interleaving	24
For more information	25
Appendix A	26
Sample Configurations for 2P ProLiant Gen8 servers	26
24 DIMM slot servers	26

Match case Limit results 1 per page

Setting Memory Interleave

Diasabling Memory Interleaving

This option is available from the Advanced Power Management menu in RBSU. Disabling memory

interleaving saves some power per DIMM, but incurs a performance penalty.

Setting Node Interleaving

This option is available from the RBSU Advanced Options menu. Enabling Node Interleaving disables the

NUMA architecture properties of the system. In NUMA configuration, each CPU core allocates memory

closest to it. If all this near memory is consumed, then it will allocate memory attached to the remote CPU

socket. When node interleaving is enabled, BIOS builds the system memory map by first using all memory

attached to the first processor and then all memory from the second processor. When Node Interleaving is

enabled, memory addresses are interleaved across the memory installed on each processor, and each

CPU core allocates memory equally from both processor sockets. Some workloads that use shared data

sets may see improved performance with this feature enabled.

Figure 15:

ROM-Based Setup Utility, Node Interleaving setting