HP Vectra VT 6/xxx HP Vectra XU 6/xxx and VT 6/xxx PCs - Technical Reference M - Page 17

The Pentium Pro processor guards against cache coherency problems by monitoring the accesses to the memory which are made by other PC devices (including DMA controllers, and a second processor, if installed) through a mechanism known as bus snooping. Associated with each cache line are two status bits which define the MESI state (modified, exclusive, shared or invalid) of the cache line. The amount of cached memory is set by Intel, at the time of manufacture, so cannot be changed. It is anticipated that Intel will offer new versions of the Pentium Pro (P6) processor with 512 KB of L2 cache memory. Upgrading the processor will then become possible as the means for changing the amount of cache memory. Extending the amount of cache memory can never have a detrimental effect on the performance. However, it can experience a law of diminishing returns, so that extending the cache memory does not have a cost-effective impact on the performance. Finding the correct amount to install is an empirical process, either by simulation, or by trial and error on the real hardware. PROCESSOR-LOCAL BUS The Processor-Local bus of the HP Vectra XU 6/150 PC and HP Vectra VT 6/150 PC is 64 bits wide, and is clocked at 60 MHz. Although carrying 64-bits of data, it is in fact composed of 141 signals. These are implemented using Intel's GTL+ technology. To reduce voltage over- and under-shoots, the signals are clamped to a 0 to 1.5 voltage range (with 60 mA per signal), and are filtered to prevent the logic edges from becoming too steep (that is, there is a minimum constraint on the rise and fall times, as well as the usual maximum constraint). The bus is implemented as a split-transaction bus. A device (such as the Pentium Pro processor) can send a request (such as asking for the contents of a given memory address) and, rather than waiting for the result, it can release the bus, to get on with other work. The target device then requests the bus when it is ready to respond, and sends the requested data packet. Up to eight transactions are allowed to be outstanding at any given time. OPTIONAL SECOND MICROPROCESSOR The support of Intel's Advanced Priority Interrupt Controller (APIC), the split-transaction bus, and the integrated L2 cache (which dispenses with the need for a proprietary bus to communicate among processors) ideally suits the Pentium Pro for the construction of multiprocessor systems. As many as four of them can be directly connected together, without the need for extra glue logic. At present, however, the HP Vectra XU 6/xxx PC only allows for dual processing capability. Not all operating systems support a second processor. Of those that do, not all uses of them increase the performance. Installing a second processor is only advantageous when the software can make use of parallel activity. In particular, you need to be running a multi-threaded operating system that supports multiprocessing (one that is MPS-ready), such as SCO-Unix, NextStep, Solaris, OS/2 SMP and Windows NT. Of these, the Windows NT operating system makes best use of the Pentium Pro's 32-bit architecture (though other operating systems will also show some benefit if 32-bit application programs are run). This is covered in the Guide to Optimizing Performance on the HP Vectra XU 6/xxx PC, and is summarized in the following table. Multi-threaded MPS-ready 32-bit operating system SCO Unix Yes Yes Yes Next Step Yes Yes Yes Sunsoft Solaris Yes No Yes OS/2 Yes No Yes Windows NT 3.5 (or greater) Yes Yes Yes Windows 95 Yes No Partial* Windows 3.x No No No DOS No No No