HP Vectra VT 6/xxx HP Vectra XU 6/xxx and VT 6/xxx PCs - Technical Reference M - Page 40

Addressing System Board Components

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ADDRESSING SYSTEM BOARD COMPONENTS This section provides more details of how the BIOS uses the system board components mentioned in the I/O port list. DMA Channel Controllers Only "I/O-to-memory" and "memory-to-I/O" transfers are allowed."I/O-to-I/O" and "memory-tomemory" transfers are disallowed by the hardware configuration. The system controller supports seven DMA channels, each with a pageregister used to extend the addressing range of the channel to 16 MB. The following table summarizes how the DMA channels are allocated. First DMA controller (used for 8-bit transfers) Channel Function 0 Available 1 SoundBlaster or ECP mode for parallel port 2 Flexible disk I/O 3 ECP mode for parallel port or SoundBlaster Second DMA controller (used for 16-bit transfers) Channel Function 4 Cascade from first DMA controller 5 SoundBlaster or Available 6 Available or SoundBlaster 7 Available Interrupt Controllers The system has two 8259A compatible interrupt controllers. They are arranged as a master interrupt controller and a slave that is cascaded through the master. The following table shows how the master and slave controllers are connected. The Interrupt Requests (IRQ) are numbered sequentially, starting with the master controller, and followed by the slave. IRQ (Interrupt Vector) IRQ0(08h) IRQ1(09h) IRQ2(0Ah) Slave IRQ IRQ8(70h) IRQ9(71h) IRQ10(72h) IRQ11(73h) IRQ12(74h) IRQ13(75h) IRQ14(76h) IRQ15(77h) Interrupt Request Description System Timer Keyboard Controller Cascade connection from INTC2 (Interrupt Controller 2) Real Time Clock Available for accessory board (ISA/PCI) SoundBlaster3, or Available for accessory board (ISA/PCI) Available for accessory board (ISA/PCI) Mouse, or ISA accessory board Co-processor IDE, or ISA accessory board 2nd IDE or ISA/PCI accessory board

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ADDRESSING SYSTEM BOARD COMPONENTS
This section provides more details of how the BIOS uses the system board components mentioned
in the I/O port list.
DMA Channel Controllers
Only “I/O-to-memory” and “memory-to-I/O” transfers are allowed.“I/O-to-I/O” and “memory-to-
memory” transfers are disallowed by the hardware configuration.
The system controller supports seven DMA channels, each with a pageregister used to extend the
addressing range of the channel to 16 MB. The following table summarizes how the DMA channels
are allocated.
First DMA controller (used for 8-bit transfers)
Channel
Function
0
1
2
3
Available
SoundBlaster or ECP mode for parallel port
Flexible disk I/O
ECP mode for parallel port or SoundBlaster
Second DMA controller (used for 16-bit transfers)
Channel
Function
4
5
6
7
Cascade from first DMA controller
SoundBlaster or Available
Available or SoundBlaster
Available
Interrupt Controllers
The system has two 8259A compatible interrupt controllers. They are arranged as a master
interrupt controller and a slave that is cascaded through the master.
The following table shows how the master and slave controllers are connected. The Interrupt
Requests (IRQ) are numbered sequentially, starting with the master controller, and followed by the
slave.
IRQ (Interrupt Vector)
Interrupt Request Description
IRQ0(08h)
System Timer
IRQ1(09h)
Keyboard Controller
IRQ2(0Ah)
Slave IRQ
Cascade connection from INTC2 (Interrupt Controller 2)
IRQ8(70h)
Real Time Clock
IRQ9(71h)
Available for accessory board (ISA/PCI)
IRQ10(72h)
SoundBlaster3, or Available for accessory board (ISA/PCI)
IRQ11(73h)
Available for accessory board (ISA/PCI)
IRQ12(74h)
Mouse, or ISA accessory board
IRQ13(75h)
Co-processor
IRQ14(76h)
IDE, or ISA accessory board
IRQ15(77h)
2nd IDE or ISA/PCI accessory board