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Interface logic signal levels PATA model - deskstar drivers

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6.4 Interface logic signal levels (PATA model) The interface logic signals have the following electrical specifications: Inputs Outputs: Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage 2.0 V min 0.8 V max. 2.4 V min. 0.5 V max. 6.4.1 Signal definition (SATA model) SATA has receivers and drivers to be connected to Tx+/ - and Rx +/- Serial data signal defines the signal names of I/O connector pin and signal name. Table 18: Interface connector pins and I/O signals No. Plug Connector pin definition S1 GND 2nd mate S2 A+ Differential signal A from Phy S3 A- Signal S4 Gnd 2nd mate S5 B- Differential signal B from Phy S6 B+ S7 Gnd 2nd mate Key and spacing separate signal and power segments P1 V33 3.3V power P2 V33 3.3V power P3 V33 3.3V power, pre-charge, 2nd Mate P4 Gnd 1st mate P5 Gnd 2nd mate P6 Gnd 2nd mate P7 V5 5V power,pre-charge,2nd Mate P8 V5 5V power Power P9 V5 5V power P10 Gnd 2nd mate P11 Reserved 1. This pin corresponding to P11 in thebackplane receptacle connector is also reserved 2. The corresponding pin to be mated with P11 in the power cable receptacle connector shall always be grounded P12 Gnd 1st mate P13 V12 12V power,pre-chage,2nd mate P14 V12 12V power P15 V12 12V power Signal Gnd RX+ RXGnd TXTX+ Gnd 3.3V 3.3V 3.3V Gnd Gnd Gnd 5V 5V 5V Gnd Reserve Gnd V12 V12 V12 I/O Input Input Output Output Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification 29

Section	Page
1.0 General	15
1.1 Introduction	15
1.2 References	15
1.3 Abbreviations	15
1.4 Caution	17
2.0 General features of the drive	19
3.0 Fixed-disk subsystem description	23
3.1 Control electronics	23
3.2 Head disk assembly	23
3.3 Actuator	23
4.0 Drive characteristics	25
4.1 Default logical drive parameters	25
4.2 Data sheet	26
4.3 World Wide Name Assignment	26
4.3.1 Drive format	26
4.3.2 Cylinder allocation	27
4.4 Performance characteristics	27
4.4.1 Command overhead	28
4.4.2 Mechanical positioning	29
4.4.3 Drive ready time	30
4.4.4 Data transfer speed	31
4.4.5 Throughput	32
4.4.6 Operating modes	33
5.0 Defect flagging strategy	35
6.0 Specification	37
6.1 Electrical Interface	37
6.1.1 Connector location	37
6.1.2 4pin DC Power connector	38
6.1.3 AT signal connector	38
6.2 Signal definitions (PATA model)	39
6.3 Signal descriptions	40
6.4 Interface logic signal levels (PATA model)	43
6.4.1 Signal definition (SATA model)	43
6.4.2 Out of band signaling (SATA model)	44
6.5 Signal timings (PATA model)	45
6.5.1 Reset timings	45
6.6 PIO timings	46
6.6.1 Write DRQ interval time	46
6.6.2 Read DRQ interval time	47
6.7 Multiword DMA timings	48
6.8 Ultra DMA timings	49
6.8.1 Initiating Read DMA	49
6.8.2 Host Pausing Read DMA	50
6.8.3 Host Terminating Read DMA	51
6.8.4 Device Terminating Read DMA	52
6.8.5 Initiating Write DMA	53
6.8.6 Device Pausing Write DMA	54
6.8.7 Device Terminating Write DMA	55
6.8.8 Host Terminating Write DMA	56
6.9 Addressing of registers	57
6.9.1 Cabling	57
7.0 Jumper Settings (PATA model)	59
7.1 Connector location	59
7.1.1 Jumper pin identification	59
7.1.2 Jumper pin assignment	60
7.1.3 Jumper positions	61
7.2 Environment	65
7.2.1 Temperature and humidity	65
7.2.2 Corrosion test	66
7.3 DC power requirements	66
7.3.1 Input voltage	66
7.3.2 Power supply current (typical)	66
7.3.3 Power supply generated ripple at drive power connector	67
7.4 Reliability	68
7.4.1 Data integrity	68
7.4.2 Cable noise interference	68
7.4.3 Start/stop cycles	68
7.4.4 Preventive maintenance	68
7.4.5 Data reliability	68
7.4.6 Required power-off sequence	68
7.5 Mechanical specifications	69
7.5.1 Physical dimensions and weight	69
7.5.2 Mounting hole locations	70
7.5.3 Connector locations	71
7.5.4 Drive mounting	72
7.5.5 Heads unload and actuator lock	72
7.6 Vibration and shock	73
7.6.1 Operating vibration	73
7.6.2 Nonoperating vibration	74
7.6.3 Operating shock	74
7.6.4 Nonoperating shock	74
7.6.5 Nonoperating rotational shock	75
7.7 Acoustics	76
7.8 Identification labels	76
7.9 Safety	77
7.9.1 UL and CSA standard conformity	77
7.9.2 German safety mark	77
7.9.3 Flammability	77
7.9.4 Safe handling	77
7.9.5 Environment	77
7.9.6 Secondary circuit protection	77
7.10 Electromagnetic compatibility	78
7.10.1 CE mark	78
7.10.2 C-TICK mark	78
7.10.3 BSMI mark	78
7.11 Packaging	78
8.0 General	79
8.1 Introduction	79
8.2 Terminology	79
8.3 Deviations from standard	79
9.0 Registers	81
9.1 Register set	81
9.2 Alternate Status Register	82
9.3 Command Register	82
9.4 Cylinder High Register	82
9.5 Cylinder Low Register	82
9.6 Data Register	83
9.7 Device Control Register	83
9.8 Drive Address Register	84
9.9 Device/Head Register	84
9.10 Error Register	85
9.11 Features Register	85
9.12 Sector Count Register	85
9.13 Sector Number Register	86
9.14 Status Register	86
10.0 General operation	89
10.1 Reset response	89
10.2 Register initialization	90
10.3 Diagnostic and Reset considerations	91
10.4 Sector Addressing Mode	92
10.4.1 Logical CHS addressing mode	92
10.4.2 LBA addressing mode	92
10.5 Power management features	93
10.5.1 Power mode	93
10.5.2 Power management commands	93
10.5.3 Standby timer	93
10.5.4 Interface capability for power modes	94
10.6 S.M.A.R.T. Function	95
10.6.1 Attributes	95
10.6.2 Attribute values	95
10.6.3 Attribute thresholds	95
10.6.4 Threshold exceeded condition	95
10.6.5 S.M.A.R.T. commands	95
10.6.6 Off-line read scanning	95
10.6.7 Error log	96
10.6.8 Self-test	96
10.7 Security Mode Feature Set	97
10.7.1 Security mode	97
10.7.2 Security level	97
10.7.3 Passwords	98
10.7.4 Operation example	98
10.7.5 Command table	101
10.8 Host Protected Area Feature	102
10.8.1 Example for operation (In LBA Mode)	102
10.8.2 Security extensions	103
10.9 Seek overlap	104
10.10 Write cache function	105
10.11 Reassign function	106
10.11.1 Auto Reassign function	106
10.12 Power-Up in Standby feature set	107
10.13 Advanced Power Management feature set (APM)	107
10.14 Automatic Acoustic Management feature set (AAM)	108
10.15 Address Offset Feature	109
10.15.1 Enable/Disable Address Offset Mode	109
10.15.2 Identify Device Data	110
10.15.3 Exceptions in Address Offset Mode	110
10.16 48-bit Address Feature Set	111
10.17 Streaming Feature Set	111
10.17.1 Streaming commands	112
10.17.2 Urgent bit	112
10.17.3 Flush to Disk bit	112
10.17.4 Not Sequential bit	112
10.17.5 Read Continuous bit	113
10.17.6 Write Continuous bit	113
10.17.7 Handle Streaming Error bit	113
10.17.8 Streaming Logs	113
11.0 Command protocol	115
11.1 PIO Data In commands	115
11.2 PIO Data Out Commands	116
11.3 Non-data commands	117
11.4 DMA commands	119
12.0 Command descriptions	121
12.1 Check Power Mode (E5h/98h)	125
12.2 Configure Stream (51h)	126
12.3 Device Configuration Overlay (B1h)	128
12.3.1 DEVICE CONFIGURATION RESTORE (Subcommand C0h)	128
12.3.2 DEVICE CONFIGURATION FREEZE LOCK (Subcommand C1h)	128
12.3.3 DEVICE CONFIGURATION IDENTIFY (Subcommand C2h)	129
12.3.4 DEVICE CONFIGURATION SET (Subcommand C3h)	129
12.4 Download Microcode (92h)	132
12.5 Execute Device Diagnostic (90h)	133
12.6 Flush Cache (E7h)	134
12.7 Flush Cache Ext (EAh)	135
12.8 Format Track (50h)	136
12.9 Format Unit (F7h)	137
12.10 Identify Device (ECh)	138
12.11 Idle (E3h/97h)	149
12.12 Idle Immediate (E1h/95h)	150
12.13 Initialize Device Parameters (91h)	151
12.14 Read Buffer (E4h)	152
12.15 Read DMA (C8h/C9h)	153
12.16 Read DMA Ext (25h)	155
12.17 Read Log Ext (2Fh)	157
12.17.1 General Purpose Log Directory	159
12.17.2 Extended Comprehensive SMART Error Log	160
12.17.3 Extended Self-test log sector	162
12.17.4 Read Stream Error log	163
12.17.5 Write Stream Error log	164
12.17.6 Streaming Performance log	165
12.18 Read Long (22h/23h)	167
12.19 Read Multiple (C4h)	169
12.20 Read Multiple Ext (29h)	171
12.21 Read Native Max ADDRESS (F8h)	173
12.22 Read Native Max Address Ext (27h)	174
12.23 Read Sectors (20h/21h)	175
12.24 Read Sector(s) Ext (24h)	177
12.25 Read Stream DMA (2Ah)	179
12.26 Read Stream PIO (2Bh)	182
12.27 Read Verify Sectors (40h/41h)	185
12.28 Read Verify Sector(s) (42h)	187
12.29 Recalibrate (1xh)	189
12.30 Security Disable Password (F6h)	190
12.31 Security Disable Password (F3h)	191
12.32 Security Erase Unit (F4h)	192
12.33 Security Freeze Lock (F5h)	194
12.34 Security Set Password (F1h)	195
12.35 Security Unlock (F2h)	197
12.36 Seek (7xh)	198
12.37 Set Features (EFh)	199
12.37.1 Set Transfer mode	200
12.37.2 Write Cache	200
12.37.3 Advanced Power Management	200
12.37.4 Automatic Acoustic Management	201
12.37.5 Set Maximum Host Interface Sector Time	202
12.38 Set Max ADDRESS (F9h)	203
12.38.1 Set Max Set Password (Feature=01h)	205
12.38.2 Set Max Lock (Feature=02h)	206
12.38.3 Set Max Unlock (Feature = 03h)	207
12.38.4 Set Max Freeze Lock (Feature = 04h)	208
12.39 Set Max Address Ext (37h)	209
12.40 Set Multiple (C6h)	211
12.41 Sleep (E6h/99h)	212
12.42 S.M.A.R.T. Function Set (B0h)	213
12.42.1 S.M.A.R.T. Function Subcommands	213
12.42.2 Device Attribute Data Structure	217
12.42.3 Device Attribute Thresholds data structure	220
12.42.4 S.M.A.R.T. Log Directory	222
12.42.5 S.M.A.R.T. summary error log sector	222
12.42.6 Self-test log data structure	224
12.42.7 Selective self-test log data structure	225
12.42.8 Error reporting	226
12.43 Standby (E2h/96h)	227
12.44 Standby Immediate (E0h/94h)	228
12.45 Write Buffer (E8h)	229
12.46 Write DMA (CAh/CBh)	230
12.47 Write DMA Ext (35h)	232
12.48 Write Log Ext (3Fh)	234
12.49 Write Long (32h/33h)	235
12.50 Write Multiple (C5h)	237
12.51 Write Multiple Ext (39h)	239
12.52 Write Sectors (30h/31h)	241
12.53 Write Sector(s) Ext (34h)	243
12.54 Write Stream DMA (3Ah)	245
12.55 Write Stream PIO (3Bh)	248

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Deskstar 7K500 and Deskstar E7K500 Hard Disk Drive Specification

6.4

Interface logic signal levels (PATA model)

The interface logic signals have the following electrical specifications:

6.4.1

Signal definition (SATA model)

SATA has receivers and drivers to be connected to Tx+/ - and Rx +/- Serial data signal defines the signal names of I/O connec-

tor pin and signal name.

Inputs

Input High Voltage

Input Low Voltage

2.0 V min

0.8 V max.

Outputs:

Output High Voltage

Output Low Voltage

2.4 V min.

0.5 V max.

Table 18: Interface connector pins and I/O signals

No.

Plug Connector pin definition

Signal

I/O

GND

2nd mate

Gnd

A+

Differential signal A from Phy

RX+

Input

A-

RX-

Input

Signal

Gnd

2nd mate

Gnd

B-

Differential signal B from Phy

TX-

Output

B+

TX+

Output

Gnd

2nd mate

Gnd

Key and spacing separate signal and power

segments

V33

3.3V power

3.3V

V33

3.3V power

3.3V

V33

3.3V power, pre-charge, 2nd Mate

3.3V

Gnd

1st mate

Gnd

2nd mate

Gnd

2nd mate

Gnd

5V power,pre-charge,2nd Mate

5V power

Power

5V power

P10

Gnd

2nd mate

Gnd

P11

Reserved

1. This pin corresponding to P11 in

thebackplane receptacle connector is also

reserved

2. The corresponding pin to be mated with

P11

in the power cable receptacle connector

shall

always be grounded

Reserve

P12

Gnd

1st mate

Gnd

P13

V12

12V power,pre-chage,2nd mate

V12

P14

V12

12V power

V12

P15

V12

12V power

V12