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Distributed VFD Registers (Read Only) Register offset 04h

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3 Reserved 0 2 Reserved 0 1 Reserved 0 0 Reserved 0 Distributed VFD Registers (Read Only) Register offset 04h Bit 0 of this register is the logic level of the input pin, E_DIST_VFD_PRESENT#. VFD Registers (Write Only) Register offset 05h Default Value Of VFD Control Register (before EEPROM is loaded): 07h Bit 0: Enable/disable the Distributed VFD TX output, i.e. Pin E_D_VFD_TX. This is a write only register and is set to "1" upon power up/reset. When bit 0 is "1", the D_VFD_TX output is enabled. Bit 1: Enable/disable the Integrated VFD TX output, i.e. Pin E_INT_VFD_TX. This is a write only register and is set to "1" upon power up/reset. When bit 1 is "1", the INT_VFD_TX output is enabled. Bit 2: How the D_VFD_TX pin behaves when enabled by bit 0. If bit 2 is "0", D_VFD_TX will be disabled when Integrated is present (i.e. when signal INT_VFD_PRESENT# is low). If bit 2 is "1", D_VFD_TX will be enabled regardless of the present of Integrated VFD. Bit 2 will be set to "1" upon power up/reset. Keyboard Control Registers (Write Only) Register offset 06h Default Value Of Keyboard Control Register (before EEPROM is loaded): 01h Bit 0: Enable/disable PS/2 keyboard on the planar. When bit 0 is set to "1", the keyboard will be enabled. SurePOS 500 Model XX3 Technical Reference, v 1.3 81 Page 45 of

Section	Page
i. Introduction	5
iii. Who should read this manual	6
iiii. Related publications	7
Chapter 1 Model Specifications	8
Model Summary	8
Notes:	9
Factory Select Feature	11
Optional Features	11
Ship Group	12
Chapter 2 Supported Devices	13
Operating System Support	14
System Software	14
POS Application Interface Drivers	14
Maintenance Package	14
Chapter 3 Architectural Overview	15
System Block Diagram	16
Main Board Block Diagram	17
Chapter 4 Physical Characteristics	19
Dimensions	19
Weights	19
Ports, Controls and Indicators	20
Port Location and Marking	20
Front Access Area (rotated)	20
Rear Tailgate	20
DISPLAY	20
Indicators	21
User Control	21
Chapter 5 Tower Logic	21
Processor	21
8245GV Memory Controller Hub, (GMCH)	21
I/O Controller Hub, Intel ICH4	22
Optional Second Video Adapter	22
Audio (Models 553 and 563)	22
Implementation Notes:	23
Network	24
Extended POS Features	24
PC Card Support (Models 553 and 563)	24
Chapter 6 Power Supply Unit	25
Power Management	25
Power Control	25
Chapter 7 LCD Panel	25
LCD Specifications	25
Touch Panel	26
DISK DRIVE	27
Chapter 8 POS I/O Specifications	27
MSR	27
External Stereo Speaker Unit	28
2x20 Displays	29
APA Display	30
Software Description	30
Boot Control	30
Setup Configuration Utility	31
Operating System	31
Maintenance Package	31
Programming Interface	32
Vital Product Data	32
Appendix A -Psychometrics	32
Classification	32
Temperature/Humidity Limits	32
Altitude Limits	32
Heat Dissipation	32
Spill/Chemical Resistance	33
Appendix B Power Specifications	34
Vibration, Shock, and Drop	34
Operating	34
Non-Operating	34
Acoustics	34
Classification	34
Noise Emission Values	35
Appendix C Standards Compliance	35
Safety/EMC	35
Appendix D Memory Map	37
I/O Map	38
PCI Configuration	40
Interrupt and DMA Assignments	41
DMA Assignments	42
Special SurePOS 500-XX3 POS Devices Interfaces	42
ASIC PCI Function 0: POS Interface - special devices	42
RW Control Registers Description	43
I/O Address Offset Description	43
Presence Sensor Control Register 0 (Read/Write) Register off	43
Function 0 Interrupt Status Register (Read/Write) Register o	44
EEPROM Control Registers (Read/Write) Register offset 02h	44
UART Control Registers (Read/Write) Register offset 03h	44
Distributed VFD Registers (Read Only) Register offset 04h	45
VFD Registers (Write Only) Register offset 05h	45
Keyboard Control Registers (Write Only) Register offset 06h	45
Appendix E ASIC PCI Function 1: POS UARTs	46
COM port/UART Assignments:	46
Configuration Registers for Function 1:	46
Interrupt Status Register B (Read Only) Offset 41h	47
Appendix F Connectors	48
Distributed Customer Display Connector	48
Speaker Connector	48
RJ45 Serial Port Connector	49
RJ45 to 9 Pin Cable Wiring	49
MSR connector	50
USB port connector (x 6)	50
USB Plus Power 12V/24V	51
Keyboard/Mouse connector	51
Microphone connector	52
Headphone Connector	52
Parallel Connector	52
External Diskette Drive Connector	52
Ethernet connector	53
External video connector	53
Cash Drawer (x2)	55
Internal Customer Display	55
Appendix G Input/Output device commands	56
VFD commands	56
Programming	67
Interface Description	67
Track data switch	67
Configuration Word	68
Byte 1, Bit 0: Carriage return Enabled	69
Byte 1, Bit 1: Raw Data Mode	70
Byte 1, Bit 2: Track 1 disabled	70
Byte 1, Bit 3: Track 2 disabled	70
Byte 1, Bit 4: Track 3 disabled	70
Byte 1, Bit 5: Hide Sentinels	70
Byte 1, Bit 6: Use Custom Configuration	70
Byte 1, Bit 7: Hide Error tracks	70
Byte 2: Track 1 start sentinel	70
Byte 3: Track 2 start sentinel	70
Byte 4: Track 3 start sentinel	71
Byte 5: End sentinel	71
Modes	71
Functional Mode	71
Command Mode	71
Update Mode	71
Reset switch	72
Command Set	72
Control commands	72
Update mode details	74
3-Track MSR	75
2-wire serial communication	75
PS/2 Keyboard communication	75
JUCC MSR	75
Usage	75
Card Speed	75

Match case Limit results 1 per page

3 Reserved 0

2 Reserved 0

1 Reserved 0

0 Reserved 0

Distributed VFD Registers (Read Only) Register offset 04h

Bit 0 of this register is the logic level of the input pin, E_DIST_VFD_PRESENT#.

VFD Registers (Write Only) Register offset 05h

Default Value Of VFD Control Register (before EEPROM is loaded): 07h

Bit 0: Enable/disable the Distributed VFD TX output, i.e. Pin E_D_VFD_TX.

This is a write only register and is

set to “1” upon power up/reset. When bit 0 is “1”, the D_VFD_TX output is enabled.

Bit 1: Enable/disable the Integrated VFD TX output, i.e. Pin E_INT_VFD_TX.

This is a write only register and

is set to “1” upon power up/reset. When bit 1 is “1”, the INT_VFD_TX output is enabled.

Bit 2: How the D_VFD_TX pin behaves when enabled by bit 0. If bit 2 is “0”, D_VFD_TX will be disabled when

Integrated is present (i.e. when signal INT_VFD_PRESENT# is low). If bit 2 is “1”, D_VFD_TX will be enabled

regardless of the present of Integrated VFD. Bit 2 will be set to “1” upon power up/reset.

Keyboard Control Registers (Write Only) Register offset 06h

Default Value Of Keyboard Control Register (before EEPROM is loaded): 01h

Bit 0: Enable/disable PS/2 keyboard on the planar. When bit 0 is set to “1”, the keyboard will be enabled.

SurePOS 500 Model XX3 Technical Reference, v 1.3

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