Intel BLKD865GLC Product Specification - Page 67
Typically, a device that does not share a PIRQ line will have
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Technical Reference Table 25. PCI Interrupt Routing Map PCI Interrupt Source PIRQA AGP connector INTA ICH5 USB UHCI controller 1 INTA SMBus controller ICH5 USB UHCI controller 2 AC '97 ICH5 Audio ICH5 LAN ICH5 USB UHCI controller 3 ICH5 USB UHCI controller 4 INTA ICH5 USB 2.0 EHCI controller PCI bus connector 1 PCI bus connector 2 PCI bus connector 3 PCI bus connector 4 (Note) PCI bus connector 5 (Note) PCI bus connector 6 (Note) INTD INTC Serial ATA Note: Desktop Board D865GBF only PIRQB INTB INTB INTB INTA INTA ICH5 PIRQ Signal Name PIRQC PIRQD PIRQE PIRQF INTB INTC INTA INTB INTB INTA INTC INTA INTD INTC INTD INTB INTA INTB INTC INTD INTA PIRQG INTB INTA INTD INTC PIRQH INTD INTC INTD INTB ✏ NOTE In PIC mode, the ICH5 can connect each PIRQ line internally to one of the IRQ signals (3, 4, 5, 6, 7, 9, 10, 11, 12, 14, and 15). Typically, a device that does not share a PIRQ line will have a unique interrupt. However, in certain interrupt-constrained situations, it is possible for two or more of the PIRQ lines to be connected to the same IRQ signal. Refer to Table 24 for the allocation of PIRQ lines to IRQ signals in APIC mode. 67