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Intel D945GCL Product Specification - Page 77

POST Code, Description of POST Operation, DXE Drivers, Runtime Phase/EFI OS Boot, PEIMs/Recovery

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Error Messages and Beep Codes Table 39. Port 80h POST Codes (continued) POST Code E7 E8 E9 EB F4 F5 F8 F9 FA 30 31 34 35 3F Description of POST Operation DXE Drivers Waiting for user input Checking password Entering BIOS setup Calling Legacy Option ROMs Runtime Phase/EFI OS Boot Entering Sleep state Exiting Sleep state EFI boot service ExitBootServices ( ) has been called EFI runtime service SetVirtualAddressMap ( ) has been called EFI runtime service ResetSystem ( ) has been called PEIMs/Recovery Crisis Recovery has initiated per User request Crisis Recovery has initiated by software (corrupt flash) Loading recovery capsule Handing off control to the recovery capsule Unable to recover 77

Section	Page
Intel® Desktop Board D945GCL Technical Product Specification	1
Revision History / Disclaimer	2
Preface	3
Intended Audience	3
What This Document Contains	3
Typographical Conventions	3
Contents	5
1 Product Description	9
1.1 Overview	10
1.1.1 Feature Summary	10
1.1.2 Board Layout	12
1.1.3 Block Diagram	14
1.2 Online Support	15
1.3 Processor	15
1.4 System Memory	16
1.4.1 Memory Configurations	18
1.5 Intel® 945G Chipset	20
1.5.1 Intel 945G Graphics Subsystem	20
1.5.2 USB	22
1.5.3 IDE Support	23
1.5.4 Real-Time Clock, CMOS SRAM, and Battery	24
1.6 PCI Express* Connectors	24
1.7 Legacy I/O Controller	25
1.7.1 Serial Port	25
1.7.2 Parallel Port	25
1.7.3 Diskette Drive Controller	25
1.7.4 Keyboard and Mouse Interface	25
1.8 Audio Subsystem	26
1.8.1 Audio Subsystem Software	26
1.8.2 Audio Connectors	26
1.8.3 6-Channel (5.1) Audio Subsystem	27
1.9 LAN Subsystem	28
1.9.1 LAN Subsystem Software	28
1.9.2 Intel® 82562G Physical Layer Interface Device	28
1.10 Hardware Management Subsystem	30
1.10.1 Hardware Monitoring and Fan Control ASIC	30
1.10.2 Chassis Intrusion and Detection	30
1.10.3 Fan Monitoring	30
1.10.4 Thermal Monitoring	31
1.11 Power Management	32
1.11.1 ACPI	32
1.11.2 Hardware Support	34
2 Technical Reference	39
2.1 Memory Resources	39
2.1.1 Addressable Memory	39
2.1.2 Memory Map	41
2.2 DMA Channels	41
2.3 Fixed I/O Map	42
2.4 PCI Configuration Space Map	43
2.5 Interrupts	44
2.6 PCI Conventional Interrupt Routing Map	45
2.7 Connectors and Headers	46
2.7.1 Back Panel Connectors	47
2.7.2 Component-side Connectors and Headers	48
2.8 Jumper Block	56
2.9 Mechanical Considerations	57
2.9.1 Form Factor	57
2.9.2 I/O Shield	58
2.10 Electrical Considerations	59
2.10.1 DC Loading	59
2.10.2 Add-in Board Considerations	59
2.10.3 Fan Header Current Capability	60
2.10.4 Power Supply Considerations	60
2.11 Thermal Considerations	61
2.12 Reliability	63
2.13 Environmental	64
3 Overview of BIOS Features	65
3.1 Introduction	65
3.2 BIOS Flash Memory Organization	66
3.3 Resource Configuration	66
3.3.1 PCI Autoconfiguration	66
3.3.2 PCI IDE Support	66
3.4 System Management BIOS (SMBIOS)	67
3.5 BIOS Updates	68
3.5.1 Language Support	68
3.5.2 Custom Splash Screen	68
3.6 Legacy USB Support	69
3.7 Boot Options	69
3.7.1 CD-ROM Boot	69
3.7.2 Network Boot	69
3.7.3 Booting Without Attached Devices	70
3.7.4 Changing the Default Boot Device During POST	70
3.8 Adjusting Boot Speed	71
3.8.1 Peripheral Selection and Configuration	71
3.8.2 BIOS Boot Optimizations	71
3.9 BIOS Security Features	72
4 Error Messages and Beep Codes	73
4.1 Speaker	73
4.2 BIOS Beep Codes	73
4.3 BIOS Error Messages	73
4.4 Port 80h POST Codes	74
5 Regulatory Compliance and Battery Disposal Information	79
5.1 Regulatory Compliance	79
5.1.1 Safety Regulations	79
5.1.2 European Union Declaration of Conformity Statement	80
5.1.3 Product Ecology Statements	81
5.1.4 EMC Regulations	85
5.1.5 Product Certification Markings (Board Level)	86