Intel MFSYS25V2 Technical Product Specification
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- Intel MFSYS25V2 | Technical Product Specification - Page 1
Intel® Compute Module MFS5520VI Technical Product Specification Intel order number: E64311-007 Revision 1.5 December, 2010 Enterprise Platforms and Services Division - Intel MFSYS25V2 | Technical Product Specification - Page 2
deviate from published specifications. Current characterized errata are available on request. Intel Corporation server baseboards support peripheral components and contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel's own chassis are designed - Intel MFSYS25V2 | Technical Product Specification - Page 3
5 3. Functional Architecture ...6 3.1 Intel® Xeon® processor 7 3.1.1 Processor Support 7 3.1.2 Mixed Processor Configuration 7 3.1.3 Turbo Mode ...9 3.1.4 Hyper-Threading...9 3.1.5 Intel® QuickPath Interconnect 9 3.1.6 Unified Retention System Support 10 3.2 Memory Subsystem 11 - Intel MFSYS25V2 | Technical Product Specification - Page 4
Table of Contents Intel® Compute Module MFS5520VI TPS 4.2 Power Connectors 23 4.3 I/O Connector Pin-out Definition 24 4.3.1 VGA Connector...24 POST Error Messages and Handling 42 Appendix D: Supported Intel® Modular Server System 46 Glossary...47 Reference Documents ...50 iv Revision - Intel MFSYS25V2 | Technical Product Specification - Page 5
5. Unified Retention System and Unified Backplate Assembly 10 Figure 6. DIMM Nomenclature...12 Figure 7. DIMM Slot Order...12 Figure 8. Integrated BMC Hardware 20 Figure 9. Recovery Jumper Blocks 31 Figure 10. Intel® Modular Server System MFSYS25 46 Revision 1.5 v Intel order number: E64311 - Intel MFSYS25V2 | Technical Product Specification - Page 6
Set 2 Table 2. Mixed Processor Configurations 8 Table 3. Mirroring DIMM Population Rules Variance across Nodes 15 Table 4. Intel® Compute Module MFS5520VI PCI Bus Segment Characteristics 18 Table 5. Video Modes ...21 Table 6. Board Connector Matrix 23 Table 7. Power Connector Pin-out (J1A1 23 - Intel MFSYS25V2 | Technical Product Specification - Page 7
Intel® Compute Module MFS5520VI TPS < This page intentionally left blank.> List of Tables Revision 1.5 vii Intel order number: E64311-007 - Intel MFSYS25V2 | Technical Product Specification - Page 8
Error Messages and Handling • Appendix D - Supported Intel® Modular Server System • Glossary • Reference Documents 1.2 Intel® Compute Module Use Disclaimer Intel® Modular Server components require adequate airflow to cool. Intel ensures through its own chassis development and testing that when these - Intel MFSYS25V2 | Technical Product Specification - Page 9
. 12 DIMMs total across 6 memory channels (3 channels per processor). Note: Mixed memory is not tested or supported. Non-ECC memory is not tested and is not supported in a server environment. ƒ Intel® 5520 Chipset IOH ƒ Intel® 82801JR I/O Controller Hub (ICH10R) External connections: ƒ Four USB - Intel MFSYS25V2 | Technical Product Specification - Page 10
L K AF003077 A Intel® 5520 Chipset I/O Hub B CPU2 DIMM Slots C Mezzanine Card Connector 1 D CPU 1 with Heatsink E Mezzanine Card Connector 2 F Midplane Power Connector G Midplane Signal Connector H Midplane Guide Pin Receptacle I CPU 1 DIMM Slots J CPU 2 Socket K Power/Fault LEDs L Power Switch - Intel MFSYS25V2 | Technical Product Specification - Page 11
TPS A B C D E FGH I AF003120 A USB ports 0 and 1 F Hard Drive Activity LED B USB ports 2 and 3 G ID LED C Video H Power button D I/O Mezzanine NIC ports 1 and I Power and Fault LEDs 2 LEDs E NIC ports 1 and 2 LEDs Figure 2. Intel® Compute Module MFS5520VI Front Panel Layout 4 Revision - Intel MFSYS25V2 | Technical Product Specification - Page 12
Intel® Compute Module MFS5520VI TPS 2.2.3 Compute Module Mechanical Drawings Product Overview 102.02 169.85 253.74 262.89 256.54 254. .40 3.27 10.16 .000 101.10 138.84 185.93 248.92 300.35 357.34 396.24 AF003121 Figure 3. Intel® Compute Module MFS5520VI - Hole and Component Positions Revision - Intel MFSYS25V2 | Technical Product Specification - Page 13
Module MFS5520VI is based on the Intel® 5520 Chipset I/O Hub (IOH) and the Intel® 82801JR ICH10 RAID. The chipset is designed for systems based on the Intel® Xeon® Processor in FC-LGA 1366 socket B package with Intel® QuickPath Interconnect (Intel® QPI). The chipset contains two main components - Intel MFSYS25V2 | Technical Product Specification - Page 14
processor specification updates published by Intel Corporation. 3.1.2 Mixed Processor Configuration The following table describes mixed processor conditions and recommended actions for the Intel is resolved. The user needs to replace the faulty part and restart the system. ƒ Major: If the "Post - Intel MFSYS25V2 | Technical Product Specification - Page 15
. ƒ Continues to boot the system successfully. Processor Intel® QuickPath Interconnect speeds not identical Major If the frequencies for all processors cannot be adjusted to be the same, then the BIOS: ƒ Logs the error. ƒ Displays "0197: Processor 0x family is not supported" message in the Error - Intel MFSYS25V2 | Technical Product Specification - Page 16
during POST. If the processor supports this feature, the BIOS Setup provides an option to enable or disable this feature. The default is enabled. 3.1.5 Intel® QuickPath Interconnect Intel® QPI is a cache-coherent, link-based interconnect specification for processor, chipset, and I/O bridge - Intel MFSYS25V2 | Technical Product Specification - Page 17
System Support The Compute Module complies with Intel's Unified Retention System (URS) and the Unified Backplate Assembly. The Compute Module ships with a made-up assembly of Independent Loading Mechanism (ILM) and Unified Backplate at each processor Cup Retaining Ring Server Board ILM and - Intel MFSYS25V2 | Technical Product Specification - Page 18
not validated and is not supported in a server environment For a complete list of supported memory for the Intel® Compute Module MFS5520VI, refer to the Tested Memory List published in the Intel® Server Configurator Tool. 3.2.2 ƒ ƒ ƒ ƒ Publishing Compute Module Memory The BIOS displays the "Total - Intel MFSYS25V2 | Technical Product Specification - Page 19
Rules The nomenclature for DIMM sockets implemented on the Intel® Compute Module MFS5520VI is detailed in the following figures. Channel A A1 A2 Processor Socket 1 Channel B Channel C B1 B2 C1 C2 Channel D D1 D2 Processor Socket 2 Channel E Channel F E1 E2 F1 F2 Figure 6. DIMM - Intel MFSYS25V2 | Technical Product Specification - Page 20
so on) in the BIOS setup are applied commonly across processor sockets. 3.2.4 Memory RAS 3.2.4.1 RAS Features The Compute Module supports the following memory RAS features: ƒ Channel Independent Mode ƒ Channel Mirroring Mode The memory RAS offered by the Intel® Xeon® Processor 5500 series and - Intel MFSYS25V2 | Technical Product Specification - Page 21
system memory. The integrated memory controller in the Intel® Xeon® Processor 5500 series and Intel® Xeon® Processor 5600 series processors be identical in terms of technology, number of ranks, and size. The BIOS setup provides an option to enable mirroring if the current DIMM population is valid - Intel MFSYS25V2 | Technical Product Specification - Page 22
Intel® Xeon® Processor 5500 series and Intel® Xeon® Processor system. ƒ Mixing RDIMMs and UDIMMs is not supported. ƒ Mixing memory type, size, speed, rank and/or vendors in the compute module is not supported. ƒ Non-ECC memory is not validated and is not supported in a server by the BIOS. ƒ When - Intel MFSYS25V2 | Technical Product Specification - Page 23
, the BIOS configures both of the processor sockets to default to the Independent Channel mode. If DIMM_D1 and DIMM_E1 are not identical, then the system switches to the Independent Channel Mode. Note: Mixed memory size, type, speed, rank and/or vendor is not validated or supported with the Intel - Intel MFSYS25V2 | Technical Product Specification - Page 24
Ethernet MAC with System Defense ƒ System Management Bus (SMBus) Specification, Version 2.0 with additional support for I2C devices ƒ Low Pin Count (LPC) interface support ƒ Firmware Hub (FWH) interface support ƒ Serial Peripheral Interface (SPI) support Revision 1.5 17 Intel order number: E64311 - Intel MFSYS25V2 | Technical Product Specification - Page 25
* Gen1 PCI I/O Card Slots x4 PCI Express* Gen1 throughput to the Intel® 5520 Chipset IOH X1 PCI Express* Gen1 throughput to an on-board Integrated * the IO Module Mezzanine connectors. Gen2 3.4.2 USB 2.0 Support The USB controller functionality integrated into ICH10R provides the Compute Module - Intel MFSYS25V2 | Technical Product Specification - Page 26
following features: ƒ Keyboard Style/BT Interface ƒ 16C550 compatible serial ports ƒ Serial IRQ support ƒ 16 GPIO ports (shared with Integrated BMC) ƒ LPC to SPI Bridge for system BIOS support ƒ SMI and PME support ƒ ACPI compliant ƒ Wake-up control The Pilot II contains an integrated KVMS subsystem - Intel MFSYS25V2 | Technical Product Specification - Page 27
Functional Architecture ƒ 2D Graphics Acceleration ƒ DDR2 graphics memory interface ƒ Up to 1600x1200 pixel resolution Intel® Compute Module MFS5520VI TPS Figure 8. Integrated BMC Hardware 20 Revision 1.5 Intel order number: E64311-007 - Intel MFSYS25V2 | Technical Product Specification - Page 28
module BIOS recognizes USB specification-compliant keyboard and mice. 3.5.3 Wake-up Control The super I/O contains functionality that allows various events to power on and power off the system. 3.6 Video Support The Compute Module includes a video controller in the on-board Server Engines - Intel MFSYS25V2 | Technical Product Specification - Page 29
the Virtualization Technology setting in the processor, the user must perform an AC power cycle for the changes to take effect. The Intel® 5520 Chipset IOH supports DMA remapping from inbound PCI Express* memory Guest Physical Address (GPA) to Host Physical Address (HPA). PCI devices are directly - Intel MFSYS25V2 | Technical Product Specification - Page 30
Intel® Compute Module MFS5520VI TPS Connector/Header Locations and Pin- , J9G1 J9J1 J9E1 J9B7 4.2 Power Connectors The power connection is obtained using a 2x2 FCI Airmax* power connector. The following table defines the power connector pin-out. Table 7. Power Connector Pin-out (J1A1) Position - Intel MFSYS25V2 | Technical Product Specification - Page 31
Connector/Header Locations and Pin-outs Intel® Compute Module MFS5520VI TPS 4.3 I/O Connector Pin-out Definition 4.3.1 VGA Connector The following table details following table details the pin-out of the Intel® I/O expansion module connector. 24 Revision 1.5 Intel order number: E64311-007 - Intel MFSYS25V2 | Technical Product Specification - Page 32
Intel® Compute Module MFS5520VI TPS Connector/Header Locations and Pin-outs Table 9. 120-pin I/O Mezzanine Card Connector Pin-out Signal Name P5V GND P3V3 P3V3 P3V3 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 Revision 1.5 25 Intel order number: E64311-007 - Intel MFSYS25V2 | Technical Product Specification - Page 33
Connector/Header Locations and Pin-outs Intel® Compute Module MFS5520VI TPS Signal Name GND GND PCIe_1_D_RXP PCIe_1_D_RXN GND GND Clk0_100M_PCIE_P Clk0_100M_PCIE_N GND GND Rsvd Rsvd Rsvd P12V 47 50 52 53 55 58 60 61 63 66 68 69 71 74 76 78 79 82 26 Revision 1.5 Intel order number: E64311-007 - Intel MFSYS25V2 | Technical Product Specification - Page 34
LED driver HSC 3 Link LED driver HSC 0 Activity LED driver HSC 1 Activity LED driver HSC 2 Activity LED driver HSC 3 Activity LED driver PCIe WAKE_N signal Reset signal (Active Low) Mezzanine Present signal (active Low) 12V power P3V3 P5V P3V3AUX Rsvd 3.3V Power 5V power Auxiliary power Reserved - Intel MFSYS25V2 | Technical Product Specification - Page 35
Connector/Header Locations and Pin-outs Intel® Compute Module MFS5520VI TPS Table 11. 40-pin I/O midplane through a 96-pin Airmax* connector (J1H1) (power is J1K1) to connect the various I/O, management, and control signals of the system. Table 12. 96-pin Midplane Signal Connector Pin-out - Intel MFSYS25V2 | Technical Product Specification - Page 36
Intel® Compute Module MFS5520VI TPS Connector/Header Locations and Pin-outs Pin Signal Name B4 XE_P1_B_TXP B5 XE_P1_C_RXN B6 XE_P1_C_TXP B7 the pin-out of the external USB connectors (J4K1, J4K2) found on the front edge of the compute module. Revision 1.5 29 Intel order number: E64311-007 - Intel MFSYS25V2 | Technical Product Specification - Page 37
with DATAH0 (Differential data line paired with DATAL0 Ground One low-profile 2x5 connector (J9B7) on the compute module provides an option to support lowprofile Intel® Z-U130 Value Solid State Drive. The pin-out of the connector is detailed in the following table. Table 15. Pin-out of Internal - Intel MFSYS25V2 | Technical Product Specification - Page 38
be used to configure, protect, or recover specific features of the server board. Pin 1 on each jumper block is denoted by an "*" or "▼". 5.1 Recovery Jumper Blocks Figure 9. Recovery Jumper Blocks BIOS Recover 3 Boot from Emergency 2 BIOS Image Default J9B9 PASSWORD Clear 32 Clear Default - Intel MFSYS25V2 | Technical Product Specification - Page 39
state. The following procedure should be followed in the event the standard Integrated BMC firmware update process fails. 1. Power down the compute module. 2. Remove the compute module from the modular server chassis. 3. Open the compute module. 32 Revision 1.5 Intel order number: E64311-007 - Intel MFSYS25V2 | Technical Product Specification - Page 40
down the compute module. 9. Remove the compute module from the server system. 10. Move jumper from the "Enabled" position (pins 2-3) to the "Disabled" position (pins 1-2). 11. Close the compute module. 12. Reinstall the compute module into the modular server chassis. 13. Power up the compute module - Intel MFSYS25V2 | Technical Product Specification - Page 41
is evaluated as part of the Intel® Modular Server System MFSYS25/MFSYS25V2/MFSYS35, which requires meeting all applicable system component regulatory requirements. Refer to the Intel® Modular Server System Technical Product Specification for a complete listing of all system and component regulatory - Intel MFSYS25V2 | Technical Product Specification - Page 42
processor specification updates published by Intel Corporation. However, the stepping of one processor cannot be greater than one stepping back of the other. ƒ Only Intel® Xeon® Processor 5500 series and Intel® Xeon® Processor 5600 series with 95 W and less Thermal Design Power (TDP) are supported - Intel MFSYS25V2 | Technical Product Specification - Page 43
lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event/reading-type table information. Sensor Type - Intel MFSYS25V2 | Technical Product Specification - Page 44
Specific 6Fh Sensor Specific 6Fh Event Offset Triggers 00 - Power down 04 - A/C lost 05 - Soft power control failure 06 - Power unit failure 00 - Timer expired, status only 01 - Hard reset Contrib. To System Status OK OK Rearm Stand-by A X A X 02 - Power down 03 - Power cycle 37 Intel - Intel MFSYS25V2 | Technical Product Specification - Page 45
Integrated BMC Sensor Tables Intel® Compute Module MFS5520VI TPS Sensor Name Physical Security SMI Timeout System Event Log System Event BB +1.1V IOH F3h Event Logging Disabled 10h System Event 12h Event/Reading Type Event Offset Triggers 08 - Timer interrupt Sensor Specific 6Fh 04 - LAN leash - Intel MFSYS25V2 | Technical Product Specification - Page 46
Processor 07h Threshold 01h Sensor Specific 6Fh Sensor Specific 01 - Limit exceeded 01 - Limit exceeded 01 - State Asserted Contrib. To System Status nc = Degraded c = Non-fatal nc = Degraded c = Non-fatal M M - - A A M M M Stand-by X - X X - X X Revision 1.5 39 Intel order number: E64311-007 - Intel MFSYS25V2 | Technical Product Specification - Page 47
Discrete 03h 01 - State Asserted 1: Inactive 2: Activation Required FRU State 2Ch Sensor Specific 6Fh 3: Activation In Progress 4: Active 5: Deactivation Required Contrib. To Rearm Stand-by System Status Non-fatal M - Fatal None None None None None M - A X 6: Deactivation In Progress - Intel MFSYS25V2 | Technical Product Specification - Page 48
?? Sensor Specific 6Fh Threshold 01h OEM ?? OEM ?? Event Offset Triggers 1: Device Present None OEM D2h OEM 72h 7: Process Started 8: Process Finished OK 9: Process Finished Fail Contrib. To Rearm Stand-by System Status None None A ? A X None A X Revision 1.5 41 Intel order number - Intel MFSYS25V2 | Technical Product Specification - Page 49
message is displayed on the Error Manager screen, an error is logged to the SEL, and the system cannot boot unless the error is resolved. The user needs to replace the faulty part and restart the system. The setup POST error Pause setting does not have any effect with this error. Table 18. POST - Intel MFSYS25V2 | Technical Product Specification - Page 50
update Processor 0x microcode update not found. Watchdog timer failed on last boot OS boot watchdog timer failure. Baseboard management controller failed self-test Baseboard management controller failed to respond Baseboard management controller in update mode Sensor data record empty System event - Intel MFSYS25V2 | Technical Product Specification - Page 51
and Handling Intel® Compute Module variables complete. Unspecified processor component has encountered a non specific error. Keyboard component services driver component encountered an illegal software state error. DXE boot services driver component encountered invalid configuration. SMM driver - Intel MFSYS25V2 | Technical Product Specification - Page 52
encountered a SERR error. ATA/ATPI ATA bus SMART not supported. ATA/ATPI ATA SMART is disabled. PCI Express component encountered a PERR error. PCI Express component encountered a SERR error. PCI Express IBIST error. DXE boot services driver Not enough memory available to shadow a legacy option ROM - Intel MFSYS25V2 | Technical Product Specification - Page 53
Server System Intel® Compute Module MFS5520VI TPS Appendix D: Supported Intel® Modular Server System The Intel® Compute Module MFS5520VI is supported in the following chassis: ƒ Intel® Modular Server System MFSYS25 ƒ Intel® Modular Server System MFSYS25V2 ƒ Intel® Modular Server System MFSYS35 - Intel MFSYS25V2 | Technical Product Specification - Page 54
IBF ICH ICMB IERR Definition Advanced Configuration and Power Interface Application Processor Advanced Programmable Interrupt Control Application Specific Integrated Circuit Advanced Server Management Interface Basic Input/Output System Built-In Self Test Baseboard Management Controller Circuitry - Intel MFSYS25V2 | Technical Product Specification - Page 55
the firmware for the platform hardware) Programmable Logic Device Platform Management Interrupt Power-On Self Test Power Supply Management Interface Pulse-Width Modulation Random Access Memory Reliability, Availability, Serviceability, Usability, and Manageability Reduced Instruction Set - Intel MFSYS25V2 | Technical Product Specification - Page 56
Intel® Compute Module MFS5520VI TPS Term SMBus SMI SMM SMS SNMP TBD TIM UART UDP UHCI UTC VID VRD Word ZIF System Management Bus Definition Server Management Interrupt (SMI is the highest priority non-maskable interrupt) Server Management Mode Server Management Software Simple Network - Intel MFSYS25V2 | Technical Product Specification - Page 57
Reference Documents Intel® Compute Module MFS5520VI TPS Reference Documents For additional information, refer to the Intel® Modular Server System Technical Product Specification. 50 Revision 1.5 Intel order number: E64311-007
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Intel
®
Compute Module MFS5520VI
Technical Product Specification
Intel order number: E64311-007
Revision 1.5
December, 2010
Enterprise Platforms and Services Division