Intel SAI2 Product Specification - Page 16

SAI2 Server Board Architecture Overview SAI2 Server Board TPS System memory begins at address 0 and is continuous (flat addressing) up to the maximum amount of DRAM installed (exception: system memory is noncontiguous in the ranges defined as memory holes using configuration registers). The server board supports both base (conventional) and extended memory. 2.4 PCI I/O Subsystem The expansion capabilities of the SAI2 server board meet the needs of file and application servers for high performance I/O by providing two PCI bus segments in the form of one 64-bit / 66-MHz bus segment and one 32-bit / 33-MHz bus segment. Each of the PCI buses comply with Revision 2.2 of the PCI Local Bus Specification. 2.4.1 64-bit / 66 MHz PCI Subsystem The 64-bit, 66-MHz, 3.3-V keyed PCI segment includes two 64-bit, 66-MHz, 3.3-V keyed PCI expansion slots that can support 66-MHz, 64/32-bit cards or 33-MHz, 64/32-bit cards. 64-bit PCI features include: • Bus speed up to 66 MHz • 3.3-V signaling environment • Burst transfers up to a peak of 528 MB per second (MBps) • 8-, 16-, 32-, or 64-bit data transfers • Plug-and-Play ready • Parity enabled 2.4.2 32-bit/33 MHz PCI Subsystem The 32-bit, 33-MHz, 5-V keyed PCI includes the following embedded devices and connectors: • Four 32-bit, 33-MHz, 5-V keyed PCI expansion slots • Integrated Intel® EtherExpress™ PRO100+ 10/100 megabit PCI Ethernet controller (Intel® 82559) • Integrated ATI Rage* XL video controller with 8 MB of on-board SGRAM • CSB5 South Bridge I/O APIC, PCI-to- Industry Standard Architecture (ISA) bridge, IDE controller, USB controller, and power management. 32-bit PCI features include: • Bus speed up to 33 MHz • 5-V signaling environment • Burst transfers up to a peak of 132 MBps • 8-, 16-, or 32-bit data transfers • Plug-and-Play ready • Parity enabled 6 Revision 1.0