MSI IMGM45D User Guide - Page 43

BIOS Setup Hardware Prefetcher The processor has a hardware prefetcher that automatically analyzes its requirements and prefetches data and instructions from the memory into the Level 2 cache that are likely to be required in the near future. This reduces the latency associated with memory reads. W hen enabled, the processor's hardware prefetcher will be enabled and allowed to automatically prefetch data and code for the processor. W hen disabled, the processor's hardware prefetcher will be disabled. Adjacent Cache Line Prefetch The processor has a hardware adjacent cache line prefetch mechanism that automatically fetches an extra 64-byte cache line whenever the processor requests for a 64-byte cache line. This reduces cache latency by making the next cache line immediately available if the processor requires it as well. W hen enabled, the processor will retrieve the currently requested cache line, as well as the subsequent cache line. W hen disabled, the processor will only retrieve the currently requested cache line. Max CPUID Value Limit The Max CPUID Value Limit BIOS feature allows you to circumvent problems with older operating systems that do not support the Intel Pentium 4 processor with Hyper-Threading Technology. W hen enabled, the processor will limit the maximum CPUID input value to 03h when queried, even if the processor supports a higher CPUID input value. When disabled, the processor will return the actual maximum CPUID input value of the processor when queried. Intel(R) Virtualization Tech Virtualization enhanced by Intel Virtualization Technology will allow a platform to run multiple operating systems and applications in independent partitions. With virtualization, one computer system can function as multiple "virtual" systems. Execute Disable Bit Capability Intel's Execute Disable Bit functionality can prevent certain classes of malicious "buffer overflow" attacks when combined with a supporting operating system. This functionality allows the processor to classify areas in memory by where application code can execute and where it cannot. W hen a malicious worm attempts to insert code in the buffer, the processor disables code execution, preventing damage or worm propagation. Core Multi-Processing CMP (Core Multi Processing) is the ability to have many independent processing cores on a single die, each with their own L1 Code & Data caches, Local APICs & thermal controls, while having a shared L2 cache, power management & bus interface. Intel multi-core architecture has a single Intel processor package that contains two or more processor "execution cores," or computational engines to enable enhanced performance and more-efficient simultaneous processing of multiple tasks. 3-7