MSI P31 NEO-F User Guide - Page 54

BIOS Setup DRAM RAS# to CAS# Delay W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is adjustable. W hen DRAM is refreshed, both rows and columns are addressed separately. This setup item allows you to determine the timing of the transition from RAS (row address strobe) to CAS (column address strobe). The less the clock cycles, the faster the DRAM performance. DRAM RAS# Precharge W hen the Configuration DRAM Timing by SPD sets to [Disabled], this field is adjustable. This setting controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. DRAM RAS# Activate to Prechar W hen the Configuration DRAM Timing by SPD sets to [Disabled], this field is adjustable. This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. DRAM TRFC W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is adjustable. This setting determines the time RFC takes to read from and write to a memory cell. DRAM TWR W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is adjustable. Minimum time interval between end of write data burst and the start of a precharge command. Allows sense amplifiers to restore data to cells. DRAM TWTR W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is adjustable. Minimum time interval between the end of write data burst and the start of a column-read command. It allows I/O gating to overdrive sense amplifiers before read command starts. DRAM TRRD W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is adjustable. Specifies the active-to-active delay of different banks. Time interval between a read and a precharge command. DRAM TRTP W hen the Configuration DRAM Timing by SPD sets to [Disabled], the field is adjustable. Time interval between a read and a precharge command. FSB/Memory Ratio This item will allow you to adjust the FSB/Ratio of the memory. 3-21