Sharp ER-A450T Service Manual - Page 25

The voltage at the (-) pin of the comparator IC7A is always maintained to 5.1V by means of the zener diode ZD2, while +24V supply voltage is divided through the resistors R114, R115 and R116, and is applied to the (+) pin. When normal +24V is in supply, 6.8V is supplied to the (+) pin, therefore, signal POFF is at a high level. When +24V supply voltage decreases due to a power off or any other reason, the voltage at the (+) pin also decreases. When +24V supply voltage drops, the voltage at the (+) pin drops below +5.1V, which causes POFF to go low, thus predicting the power-off situation. CKDC8 RESETS R245 10K STOP VDD 14 9 8 10 IC12C 74HC00S C188 1000P RAS3 VDD 14 1 3 2 IC12A 74HC00S C86 1000P VDD 14 4 6 5 IC12B 74HC00S /RESET /(RAS3./RESET) C175 1000P The STOP signal from the CPU is converted into the RESETS signal by the CKDC8. The RESETS signal from the CKDC8 is converted into the RESET signal at the gate backed-up by the VRAM power, performing the system reset. 5. Memory control 1) Memory map All range memory map 000000H Internal I/O (*1) External I/O (*2) 1C0000H Memory image area (*3) RAM area (10M byte) 0 page memory map 000000H 004000H ROM image area 32KB 008000H RAM image area slightly smaller than32KB 00F800H 00FFFFH RAM image area NOT USE 00FE80H Internal I/O area 1BFFFFH 1FFFFFH RAM area 00FF80H 00FFFFH External I/O area (0 page) Fig. 5-2 • ROM image area: Image is formed in ROM area address C00000H to C07FFFH. This area is identical to IPL ROM area which will beseparately developed. • RAM image area: Image is formed in RAM area address 1F0000H to 1F7E7FH. ( Note) Note: Image can be formed in lower 32KB of RAS2. ROM area memory map C00000H ROS1 (512K Byte) C00000H ROM area (3M byte) FFFFFFH Expansion I/O area (1M byte) Fig. 5-1 ( 1) "Internal I/O" means the registers in the H8/510. ( 2) "External I/O" means the base system I/O area to be addressed in page 0. ( 3) "Memory image area" means the lower 32KB of ROM area which is projected to 000000H ~ 007FFFH for allowing reset start and other vector addressing, or the lower 32KB of ROM area which is projected to 008000H ~ 00FE7FH for allowing 0 page addressing of work RAM area. ( 4) "Expansion I/O" means expansion I/O device area which is addressed to area other than page 0. 4 - 17 C80000H CA0000H ROS2 (Not used) D00000H ROS3 NOT USE EFFFFFH Fig. 5-3