Sony HCD-MD515 Service Manual - Page 57

Board, Ic121, Cxd2652ar, Digital, Signal, Processor, Digital, Servo, Efm/acirc, Encoder/decoder,

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Page 57 highlights

• BD (MD) BOARD IC121 CXD2652AR • (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK • PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER) Pin No. Pin Name I/O 1 MNT0 (FOK) O 2 MNT1(SHCK) O 3 MNT2 (XBUSY) O 4 MNT3 (SLOC) O 5 SWDT I 6 SCLK I 7 XLAT I 8 SRDT O (3) 9 SENS O (3) 10 XRST I 11 SQSY O 12 DQSY O 13 RECP I 14 XINT O 15 TX I 16 OSCI I 17 OSCO O 18 XTSL I 19 RVDD - 20 RVSS - 21 DIN I 22 DOUT O 23 ADDT I 24 DADT O 25 LRCK O 26 XBCK O 27 FS256 O 28 DVDD - 29 to 32 A03 to A00 O 33 A10 O 34 to 38 A04 to A08 O 39 A11 O 40 DVSS - 41 XOE O 42 XCAS O 43 A09 O 44 XRAS O 45 XWE O Function Focus OK signal output to the system controller (IC316) "H" is output when focus is on Track jump detection signal output to the system controller (IC316) Monitor 2 signal output to the system controller (IC316) Monitor 3 signal output to the system controller (IC316) Writing data signal input from the system controller (IC316) Serial clock signal input from the system controller (IC316) Serial latch signal input from the system controller (IC316) Reading data signal output to the system controller (IC316) Internal status (SENSE) output to the system controller (IC316) Reset signal input from the system controller (IC316) "L": reset Subcode Q sync (SCOR) output to the system controller (IC316) "L" is output every 13.3 msec Almost all, "H" is output Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC316) "L" is output every 13.3 msec Almost all, "H" is output Laser power selection signal input from the system controller (IC316) "H": recording mode, "L": playback mode Interrupt status output to the system controller (IC316) Recording data output enable signal input from the system controller (IC316) Writing data transmission timing input (Also serves as the magnetic head on/off output) System clock signal (512Fs=22.5792 MHz) input from the A/D, D/A converter (IC201) System clock signal (512Fs=22.5792 MHz) output terminal Not used (open) Input terminal for the system clock frequency setting "L": 45.1584 MHz, "H": 22.5792 MHz (fixed at "H" in this set) Power supply terminal (+3.3V) (digital system) Ground terminal (digital system) Digital audio signal input terminal when recording mode (for optical in) Digital audio signal output terminal when playback mode (for optical out) Not used Recording data input from the A/D, D/A converter (IC201) Playback data output to the A/D, D/A converter (IC201) L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC201) Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC201) Clock signal (11.2896 MHz) output terminal Not used (open) Power supply terminal (+3.3V) (digital system) Address signal output to the D-RAM (IC124) Address signal output to the external D-RAM Not used (open) Address signal output to the D-RAM (IC124) Address signal output to the external D-RAM Not used (open) Ground terminal (digital system) Output enable signal output to the D-RAM (IC124) Column address strobe signal output to the D-RAM (IC124) Address signal output to the D-RAM (IC124) Row address strobe signal output to the D-RAM (IC124) Write enable signal output to the D-RAM (IC124) * O (3) for 3-state output in the column I/O. - 93 -

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– 93 –
•
BD
(MD)
BOARD
IC121
CXD2652AR
•
(DIGITAL
SIGNAL
PROCESSOR,
DIGITAL
SERVO
PROCESSOR,
EFM/ACIRC
ENCODER/DECODER,
SHOCK
•
PROOF
MEMORY
CONTROLLER,
ATRAC
ENCODER/DECODER)
Pin No.
Pin Name
I/O
Function
* O (3) for 3-state output in the column I/O.
1
MNT0 (FOK)
O
Focus OK signal output to the system controller (IC316)
“H” is output when focus is on
2
MNT1(SHCK)
O
Track jump detection signal output to the system controller (IC316)
3
MNT2 (XBUSY)
O
Monitor 2 signal output to the system controller (IC316)
4
MNT3 (SLOC)
O
Monitor 3 signal output to the system controller (IC316)
5
SWDT
I
Writing data signal input from the system controller (IC316)
6
SCLK
I
Serial clock signal input from the system controller (IC316)
7
XLAT
I
Serial latch signal input from the system controller (IC316)
8
SRDT
O (3)
Reading data signal output to the system controller (IC316)
9
SENS
O (3)
Internal status (SENSE) output to the system controller (IC316)
10
XRST
I
Reset signal input from the system controller (IC316)
“L”: reset
11
SQSY
O
Subcode Q sync (SCOR) output to the system controller (IC316)
“L” is output every 13.3 msec
Almost all, “H” is output
12
DQSY
O
Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC316)
“L” is output every 13.3 msec
Almost all, “H” is output
13
RECP
I
Laser power selection signal input from the system controller (IC316)
“H”: recording mode, “L”: playback mode
14
XINT
O
Interrupt status output to the system controller (IC316)
15
TX
I
Recording data output enable signal input from the system controller (IC316)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
16
OSCI
I
System clock signal (512Fs=22.5792 MHz) input from the A/D, D/A converter (IC201)
17
OSCO
O
System clock signal (512Fs=22.5792 MHz) output terminal
Not used (open)
18
XTSL
I
Input terminal for the system clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)
19
RVDD
—
Power supply terminal (+3.3V) (digital system)
20
RVSS
—
Ground terminal (digital system)
21
DIN
I
Digital audio signal input terminal when recording mode (for optical in)
22
DOUT
O
Digital audio signal output terminal when playback mode (for optical out)
Not used
23
ADDT
I
Recording data input from the A/D, D/A converter (IC201)
24
DADT
O
Playback data output to the A/D, D/A converter (IC201)
25
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC201)
26
XBCK
O
Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC201)
27
FS256
O
Clock signal (11.2896 MHz) output terminal
Not used (open)
28
DVDD
—
Power supply terminal (+3.3V) (digital system)
29 to 32
A03 to A00
O
Address signal output to the D-RAM (IC124)
33
A10
O
Address signal output to the external D-RAM
Not used (open)
34 to 38
A04 to A08
O
Address signal output to the D-RAM (IC124)
39
A11
O
Address signal output to the external D-RAM
Not used (open)
40
DVSS
—
Ground terminal (digital system)
41
XOE
O
Output enable signal output to the D-RAM (IC124)
42
XCAS
O
Column address strobe signal output to the D-RAM (IC124)
43
A09
O
Address signal output to the D-RAM (IC124)
44
XRAS
O
Row address strobe signal output to the D-RAM (IC124)
45
XWE
O
Write enable signal output to the D-RAM (IC124)