ASRock Z87 Extreme6/ac User Manual - Page 87

DRAM Configuration, DRAM Tweaker, CAS# Latency tCL, Row Precharge Time tRP, RAS# Active Time tRAS

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DRAM Configuration Z87 Extreme6/ac / Z87 Extreme6 DRAM Tweaker Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and apply your new settings. CAS# Latency (tCL) The time between sending a column address to the memory and the beginning of the data in response. RAS# to CAS# Delay (tRCD) The number of clock cycles required between the opening of a row of memory and accessing columns within it. Row Precharge Time (tRP) The number of clock cycles required between the issuing of the precharge command and opening the next row. RAS# Active Time (tRAS) The number of clock cycles required between a bank active command and issuing the precharge command. 81 English

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81
English
Z
8
7 Extreme
6/ac /
Z
8
7 Extreme
6
DRAM Configuration
DRAM Tweaker
Fine tune the DRAM settings by leaving marks in checkboxes. Click OK to confirm and
apply your new settings.
CAS# Latency (tCL)
°e time between sending a column address to the memory and the beginning of the data
in response.
RAS# to CAS# Delay (tRCD)
°e number of clock cycles required between the opening of a row of memory and
accessing columns within it.
Row Precharge Time (tRP)
°e number of clock cycles required between the issuing of the precharge command
and opening the next row.
RAS# Active Time (tRAS)
°e number of clock cycles required between a bank active command and issuing the
precharge command.