Acer AW2000ht-AW170ht F1 Acer AW2000ht w AW170htx F1 Server Service Guide - Page 59

Lockstep mode • In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel 1 and Channel 2. This is done to support SDDC for DRAM devices with 8-bit wide data ports. The same address is used on both channels such that an address error on any channel is detectable by ECC. Lockstep Channel mode is the only RAS mode that supports x8 SDDC. • Channel 3 has no function and cannot be populated in this mode. • Follow the population rules described in independent mode. • DIMM modules installed in channels 1 and 2 must be identical - 1A and 2A should be the same type, size and manufacturer. 1B and 2B memory should be the same type, size and manufacturer. However, it is not necessary for slot A to have the same memory module as slot B within a channel. • The same rule applies to processor 2. Memory population for lockstep mode Single processor configuration Configuration A B Single processor Processor 1 P1DIMM slots Channel 1 Channel 2 Channel 3 1B 1A 2B 2A 3B 3A X X NA NA X X X X NA NA Dual processor configuration Configuration A B C D Dual processors Processor 1 P1DIMM slots Channel 1 Channel 2 Channel 3 1B 1A 2B 2A 3B 3A X X NA NA X X NA NA X X X X NA NA X X X X NA NA Processor 2 P2DIMM slots Channel 1 Channel 2 Channel 3 1B 1A 2B 2A 3B 3A NA NA X X NA NA X X NA NA X X X X NA NA Notes: 1. Place DIMMs in "X" location. 2. DIMM population must correspond to the above tables. 3. DIMM modules support 1 GB, 2 GB, 4 GB and 8 GB DIMMS. 4. The size of each DIMM must be the same across the configuration. 5. Do not mix UDIMMs with RDIMMs. Sparing mode (only supported on Intel Xeon Processor 5600 Series CPUs) • In this mode, if the system detects degrading memory and did not crash, the data in the failed channel will be copied to the spare channel. The failed channel is then isolated and the spare channel becomes active. However, any uncorrectable error that happens before the isolation will still cause the system to stop normal operation. • Channel 3 is the spare channel. Therefore, the effective size will be reduced by one-third. • Follow the population rules described in the independent mode. • Sparing mode requires that all three channels use identical DIMMs. 1A, 2A and 3A should be the same type, size and manufacturer, likewise for 1B, 2B and 3B. The same rule applies to processor 2. • Intel Xeon Processor 5500 Series CPU does NOT support the memory sparing mode. Hardware removal and installation 53