Asus A8V-E Deluxe A8V-E Deluxe user's manual English Version E1781 - Page 85

4.4.2 Chipset Advanced Phoenix-Award BIOS CMOS Setup Utility Chipset Select Menu DRAM Configuration Upstream LDT Bus Width Downstream LDT Bus Width LDT Bus Frequency VLink Mode Selection PEG Data Scrambling PE0-PE3 Data Scrambling Init Display First Chipset Vcore Adjustment [16 bit] [16 bit] [Auto] [By Auto] [Auto] [Enable] [PCI Slot [+1.6 V] Item Specific Help DRAM timing and control F1:Help ESC: Exit ↑↓ : Select Item →←: Select Menu -/+: Change Value Enter: Select Sub-menu F5: Setup Defaults F10: Save and Exit DRAM Configuration The items in this sub-menu show the DRAM-related information auto-detected by the BIOS. Advanced Phoenix-Award BIOS CMOS Setup Utility DRAM Configuration Current DRAM Frequency Max Memclock (MHz) CAS# latency (Tcl) RAS# to CAS# delay (Trcd) Min RAS# active time(Tras) Row precharge Time (Trp) Master ECC Enable 166 MHz [Auto] [Auto] [Auto] [Auto] [Auto] [Enabled] Select Menu Item Specific Help Place an artificial memory clock limit on the system. Memory is prevented from running faster than this frequency. F1:Help ESC: Exit ↑↓ : Select Item →←: Select Menu -/+: Change Value Enter: Select Sub-menu F5: Setup Defaults F10: Save and Exit Current DRAM Frequency Shows the Transfer mode. This item is not configurable. Max Memclock (MHz) [Auto] Sets the maximum operating memory clock. Configuration options: [Auto] [DDR200] [DDR266] [DDR333] [DDR400] ASUS A8V-E Deluxe 4-19