Asus A8V-E Deluxe A8V-E Deluxe user's manual English Version E1781 - Page 86
Upstream LDT Bus Width [16 bit], Downstream LDT Bus Width [16 bit], LDT Bus Frequency [Auto], VLink
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CAS# latency (Tcl) [Auto] Controls the latency between the SDRAM read command and the time the data actually becomes available. Configuration options: [Auto] [2.0] [2.5] [3.0] RAS# to CAS# delay (Trcd) [Auto] Controls the latency between the DDR SDRAM active command and the read/write command. Configuration options: [Auto] [2] [3] [4] [5] [6] [7] Min RAS# active time (Tras) [Auto] Sets the minimum RAS# active time. Configuration options: [Auto] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] Row precharge Time (Trp) [Auto] Sets the Row precharge time. Configuration options: [Auto] [2] [3] [4] [5] [6] Master ECC Enable [Enabled] Enables or disables the Master ECC feature. Configuration options: [Disabled] [Enabled] Upstream LDT Bus Width [16 bit] Sets the upstream Lightning Data Transport (LDT) Bus Width. Configuration options: [ 8 bit] [16 bit] Downstream LDT Bus Width [16 bit] Sets the downstream Lightning Data Transport (LDT) Bus Width. Configuration options: [ 8 bit] [16 bit] LDT Bus Frequency [Auto] Sets the Lightning Data Transport (LDT) Bus frequency. Configuration options: [Auto] [1 GHz] [800 MHz] [600 MHz] [400 MHz] [200 MHz] VLink Mode Selection [By Auto] Sets the VLink mode. Configuration options: [By Auto] [Mode 0] [Mode 1] [Mode 2] [Mode 3] [Mode 4] PEG Data Scrambling [Auto] Disables or enables the PCI Express™ graphics data scrambling. Configuration options: [Auto] [Disable] [Enable] 4-20 Chapter 4: BIOS setup