Biostar A780L3B Bios Setup - Page 35
XOR of Address bits [20:16, 6] Default / XOR of Address bits
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A780L3B BIOS Manual TRRD Options: Auto (Default) / 4~7 CLK tWT R Options: Auto (Default) / 4~7 CLK tRFC0 / tRFC1 / tRFC2 / tRFC3 Options: Auto (Default) / 90ns / 110ns / 160ns / 300ns / 350ns Memory Configuration BIOS SETUP UTILITY Performance Memory Configuration Bank Interleaving Channel Interleaving Enable Clock to All DIMMs MemClk Tristate C3/ATLVID Memory Hole Remapping DCT Unganged Mode Power Down Enable Page Smashing > ECC Configuration [Auto] [XOR of Address bit] [Disabled] [Disabled] [Enabled] [Always] [Disabled] [Disabled] Enable Bank Memory Interleaving Select Screen Select Item +- Change Option F1 General Help F10 Save and Exit ESC Exit vxx.xx (C)Copyright 1985-200x, American Megatrends, Inc. Bank Interleaving Bank Interleaving is an advanced chipset technique used to improve memory performance. Memory interleaving increases bandwidth by allowing simultaneous access to more than one piece of memory. Options: Auto (Default) Channel Interleaving This item allows you to control the DDR2 dual-channel function. Options: XOR of Address bits [20:16, 6] (Default) / XOR of Address bits [20:16, 9] / Address bits 6 / Address bits 12 / Disabled 34