Biostar IDEQ 200TB iDEQ 200T BIOS setup guide - Page 13

P4TBA BIOS Setup 4 Advanced Chipset Features This submenu allows you to configure the specific features of the chipset installed on your system. This chipset manage bus speeds and access to system memory resources, such as DRAM. It also coordinates communications with the PCI bus. The default settings that came with your system have been optimized and therefore should not be changed unless you are suspicious that the settings have been changed incorrectly. Figure 4. Advanced Chipset Setup DRAM Timing Selectable When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. The Choices: By SPD (Default), Manual CAS Latency Time When synchronous DRAM is installed, the number of clock cycles of CAS latency depends on the DRAM timing. The Choices: 2 (Default), 2.5, 3.0. Active to Precharge Delay This item controls the number of DRAM clocks to activate the precharge delay. The Choices: 8 (Default), 7, 6, 5. 12