Gigabyte GA-970A-UD3 Manual - Page 37

CPU Host Clock Control, CPU Frequency MHz, Set Memory Clock, Memory Clock, DCTs Mode, DDR3 Timing

Page 37 highlights

DRAM Configuration CMOS Setup Utility-Copyright (C) 1984-2011 Award Software DRAM Configuration CPU Host Clock Control x CPU Frequency(MHz) Set Memory Clock x Memory Clock DCTs Mode DDR3 Timing Items x 1T/2T Command Timing x CAS# latency x RAS to CAS R/W Delay x Row Precharge Time x Minimum RAS Active Time x TwTr Command Delay x Trfc1 for DIMM1, DIMM3 x Trfc0 for DIMM2, DIMM4 x Write Recovery Time x Precharge Time x Row Cycle Time x RAS to RAS Delay **DCTs Drive Strength** [Auto] 200 [Auto] x6.66 1333Mhz [Unganged] [Auto] SPD Auto Auto -- -- Auto 9T 9T Auto 9T 9T Auto 9T 9T Auto 24T 24T Auto 5T 5T Auto 110ns 110ns Auto -- -- Auto 10T 10T Auto 5T 5T Auto 33T 33T Auto 4T 4T DCT0 DCT1 Item Help Menu Level  Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General Help F7: Optimized Defaults CMOS Setup Utility-Copyright (C) 1984-2011 Award Software DRAM Configuration ProcOdt(ohms) DQS Drive Strength Data Drive Strength MEMCLK Drive Strength Addr/Cmd Drive Strength CS/ODT Drive Strength CKE Drive Strength **DCTs Addr/Cmd Timing** Addr/Cmd Setup Time Addr/Cmd Fine Delay CS/ODT Setup Time CS/ODT Fine Delay CKE Setup Time CKE Fine Delay [Auto] 60 [Auto] 240 [Auto] 1.0x [Auto] 1.5x [Auto] 1.0x [Auto] 1.5x [Auto] 1.5x [Auto] 1.5x [Auto] 1.5x [Auto] 2.0x [Auto] 1.5x [Auto] 2.0x [Auto] 1.5x [Auto] 2.0x DCT0 DCT1 [Auto] 1/2T [Auto] 1/2T [Auto] 0/64 [Auto] 0/64 [Auto] 1/2T [Auto] 1/2T [Auto] 0/64 [Auto] 0/64 [Auto] 1/2T [Auto] 1/2T [Auto] 0/64 [Auto] 0/64 Item Help Menu Level  Channel interleaving Bank Interleaving DQS Training Control CKE Power Down Mode Memclock tri-stating [Enabled] [Enabled] [Skip DQS] [Disabled] [Disabled] Move Enter: Select F5: Previous Values +/-/PU/PD: Value F10: Save F6: Fail-Safe Defaults ESC: Exit F1: General Help F7: Optimized Defaults CPU Host Clock Control, CPU Frequency (MHz), Set Memory Clock, Memory Clock The settings under the four items above are synchronous to those under the same items on the MB Intelligent Tweaker(M.I.T.) main menu. DCTs Mode Allows you to set memory control mode. Ganged Sets memory control mode to single dual-channel. Unganged Sets memory control mode to two single-channel. (Default) DDR3 Timing Items Manual allows all DDR3 Timing items below to be configurable. Options are: Auto (default), Manual. - 37 - BIOS Setup

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- 37 -
BIOS Setup
DRAM Configuration
CPU Host Clock Control, CPU Frequency (MHz), Set Memory Clock, Memory Clock
The settings under the four items above are synchronous to those under the same items on the
MB In-
telligent Tweaker(M.I.T.)
main menu.
DCTs Mode
Allows you to set memory control mode.
Ganged
Sets memory control mode to single dual-channel.
Unganged
Sets memory control mode to two single-channel. (Default)
DDR3 Timing Items
Manual
allows all DDR3 Timing items below to be configurable.
Options are: Auto (default), Manual.
CMOS Setup Utility-Copyright (C) 1984-2011 Award Software
DRAM Configuration
CPU Host Clock Control
[Auto]
x
CPU Frequency(MHz)
200
Set Memory Clock
[Auto]
x
Memory Clock
x6.66
1333Mhz
DCTs Mode
[Unganged]
DDR3 Timing Items
[Auto]
SPD
Auto
x
1T/2T Command Timing
Auto
--
--
x
CAS# latency
Auto
9T
9T
x
RAS to CAS R/W Delay
Auto
9T
9T
x
Row Precharge Time
Auto
9T
9T
x
Minimum RAS Active Time
Auto
24T
24T
x
TwTr Command Delay
Auto
5T
5T
x
Trfc1 for DIMM1, DIMM3
Auto
110ns
110ns
x
Trfc0 for DIMM2, DIMM4
Auto
--
--
x
Write Recovery Time
Auto
10T
10T
x
Precharge Time
Auto
5T
5T
x
Row Cycle Time
Auto
33T
33T
x
RAS to RAS Delay
Auto
4T
4T
**
DCTs Drive Strength
**
DCT0
DCT1
higf
: Move
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Item Help
Menu Level

CMOS Setup Utility-Copyright (C) 1984-2011 Award Software
DRAM Configuration
higf
: Move
Enter: Select
+/-/PU/PD: Value
F10: Save
ESC: Exit
F1: General Help
F5: Previous Values
F6: Fail-Safe Defaults
F7: Optimized Defaults
Item Help
Menu Level

ProcOdt(ohms)
[Auto]
60
[Auto]
240
DQS Drive Strength
[Auto]
1.0x
[Auto]
1.5x
Data Drive Strength
[Auto]
1.0x
[Auto]
1.5x
MEMCLK Drive Strength
[Auto]
1.5x
[Auto]
1.5x
Addr/Cmd Drive Strength
[Auto]
1.5x
[Auto]
2.0x
CS/ODT Drive Strength
[Auto]
1.5x
[Auto]
2.0x
CKE Drive Strength
[Auto]
1.5x
[Auto]
2.0x
**
DCTs Addr/Cmd Timing
**
DCT0
DCT1
Addr/Cmd Setup Time
[Auto]
1/2T
[Auto]
1/2T
Addr/Cmd Fine Delay
[Auto]
0/64
[Auto]
0/64
CS/ODT Setup Time
[Auto]
1/2T
[Auto]
1/2T
CS/ODT Fine Delay
[Auto]
0/64
[Auto]
0/64
CKE Setup Time
[Auto]
1/2T
[Auto]
1/2T
CKE Fine Delay
[Auto]
0/64
[Auto]
0/64
Channel interleaving
[Enabled]
Bank Interleaving
[Enabled]
DQS Training Control
[Skip DQS]
CKE Power Down Mode
[Disabled]
Memclock tri-stating
[Disabled]