Gigabyte GA-G1975X Manual - Page 3

Initialize the APIC for P6 class CPU. - no display

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POST (hex) 40h 43h 47h 49h 4Eh 50h 52h 55h 57h 59h 5Bh 5Dh 60h 65h 67h 69h 6Bh 6Dh 6Fh 73h Description Test 8259 interrupt mask bits for channel 2. Test 8259 functionality. Initialize EISA slot 1. Calculate total memory by testing the last double word of each 64K page. 2. Program write allocation for AMD K5 CPU. 1. Program MTRR of M1 CPU 2. Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range. 3. Initialize the APIC for P6 class CPU. 4. On MP platform, adjust the cacheable range to smaller one in case the cacheable ranges between each CPU are not identical. Initialize USB Test all memory (clear all extended memory to 0) Display number of processors (multi-processor platform) 1. Display PnP logo 2. Early ISA PnP initialization -Assign CSN to every ISA PnP device. Initialize the combined Trend Anti-Virus code. (Optional Feature) Show message for entering AWDFLASH.EXE from FDD (optional) 1. Initialize Init_Onboard_Super_IO switch. 2. Initialize Init_Onbaord_AUDIO switch. Okay to enter Setup utility; i.e. not until this POST stage can users enter the CMOS setup utility. Initialize PS/2 Mouse Prepare memory size information for function call: INT 15h ax=E820h Turn on L2 cache Program chipset registers according to items described in Setup & Auto-configuration table. 1. Assign resources to all ISA PnP devices. 2. Auto assign ports to onboard COM ports if the corresponding item in Setup is set to "AUTO". 1. Initialize floppy controller 2. Set up floppy related fields in 40:hardware. (Optional Feature) Enter AWDFLASH.EXE if : -AWDFLASH is found in floppy drive. GA-G1975X Post Code Definition 11/14/2005 3

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GA-G1975X Post Code Definition
11/14/2005
3
POST (hex)
Description
40h
Test 8259 interrupt mask bits for channel 2.
43h
Test 8259 functionality.
47h
Initialize EISA slot
49h
1.
Calculate total memory by testing the last double word of each 64K page.
2.
Program write allocation for AMD K5 CPU.
4Eh
1.
Program MTRR of M1 CPU
2.
Initialize L2 cache for P6 class CPU & program CPU with proper cacheable range.
3.
Initialize the APIC for P6 class CPU.
4.
On MP platform, adjust the cacheable range to smaller one in case the cacheable
ranges between each CPU are not identical.
50h
Initialize USB
52h
Test all memory (clear all extended memory to 0)
55h
Display number of processors (multi-processor platform)
57h
1.
Display PnP logo
2.
Early ISA PnP initialization
-Assign CSN to every ISA PnP device.
59h
Initialize the combined Trend Anti-Virus code.
5Bh
(Optional Feature)
Show message for entering AWDFLASH.EXE from FDD (optional)
5Dh
1.
Initialize Init_Onboard_Super_IO switch.
2.
Initialize Init_Onbaord_AUDIO switch.
60h
Okay to enter Setup utility; i.e. not until this POST stage can users
enter the CMOS setup utility.
65h
Initialize PS/2 Mouse
67h
Prepare memory size information for function call:
INT 15h ax=E820h
69h
Turn on L2 cache
6Bh
Program chipset registers according to items described in Setup &
Auto-configuration table.
6Dh
1.
Assign resources to all ISA PnP devices.
2.
Auto assign ports to onboard COM ports if the corresponding item in Setup is set to
“AUTO”.
6Fh
1.
Initialize floppy controller
2.
Set up floppy related fields in 40:hardware.
73h
(Optional Feature)
Enter AWDFLASH.EXE if :
-AWDFLASH is found in floppy drive.