Gigabyte GA-P55-UD6 Manual - Page 124

POST Error Code, POST hex, Description

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5-4 POST Error Code POST (hex) CFh C0h C1h C3h C5h 01h 02h 03h 05h 07h 08h 0Ah 0Eh 10h 12h 14h 16h 18h 1Bh 1Dh 23h Description Test CMOS R/W functionalitySix Modules Early chipset initialization: -Disable shadow RAM - Program basic chipset registers Detect memory - Auto-detection of DRAM size, type and ECC Expand compressed BIOS code to DRAM Call chipset hook to copy BIOS back to E000 & F000 shadow RAM Expand the Xgroup codes locating in physical address 1000:0 DualBIOS init (optional) Initial Superio_Early_Init switch 1. Blank out screen 2. Clear CMOS error flag 1. Clear 8042 interface 2. Initialize 8042 self-test 1. Test special keyboard controller for Winbond 977 series Super I/O chips 2. Enable keyboard interface 1. Disable PS/2 mouse interface (optional) 2. Auto detect ports for keyboard & mouse followed by a port & interface swap (optional) 3. Reset keyboard Super I/O chips Test F000h segment shadow to see whether it is R/W-able or not. If test fails, keep beeping the speaker Auto detect flash type to load appropriate flash R/W codes into the run time area in F000 for ESCD & DMI support Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time clock power status, and then check for override Program chipset default values into chipset. Chipset default values are MODBINable by OEM customers Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also POST 26h Detect CPU information including brand, SMI type and CPU level Initial interrupts vector table. If no special specified, all H/W interrupts are directed to SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR Initial EARLY_PM_INIT switch 1. Check validity of RTC value: e.g. a value of 5Ah is an invalid value for RTC minute 2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value instead Appendix - 124 -

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Appendix
- 124 -
5-4
POST Error Code
POST (hex)
Description
CFh
Test CMOS R/W functionalitySix
Modules
C0h
Early chipset initialization:
-Disable shadow RAM
- Program basic chipset registers
C1h
Detect memory
- Auto-detection of DRAM size, type and ECC
C3h
Expand compressed BIOS code to DRAM
C5h
Call chipset hook to copy BIOS back to E000 & F000 shadow RAM
01h
Expand the Xgroup codes locating in physical address 1000:0
02h
DualBIOS init (optional)
03h
Initial Superio_Early_Init switch
05h
1. Blank out screen
2. Clear CMOS error flag
07h
1. Clear 8042 interface
2. Initialize 8042 self-test
08h
1. Test special keyboard controller for Winbond 977 series Super I/O chips
2. Enable keyboard interface
0Ah
1. Disable PS/2 mouse interface (optional)
2. Auto detect ports for keyboard & mouse followed by a port & interface swap (op-
tional)
3. Reset keyboard Super I/O chips
0Eh
Test F000h segment shadow to see whether it is R/W-able or not. If test fails, keep
beeping the speaker
10h
Auto detect flash type to load appropriate flash R/W codes into the run time area in
F000 for ESCD & DMI support
12h
Use walking 1's algorithm to check out interface in CMOS circuitry. Also set real-time
clock power status, and then check for override
14h
Program chipset default values into chipset. Chipset default values are MODBINable
by OEM customers
16h
Initial onboard clock generator if Early_Init_Onboard_Generator is defined. See also
POST 26h
18h
Detect CPU information including brand, SMI type and CPU level
1Bh
Initial interrupts vector table. If no special specified, all H/W interrupts are directed to
SPURIOUS_INT_HDLR & S/W interrupts to SPURIOUS_soft_HDLR
1Dh
Initial EARLY_PM_INIT switch
23h
1. Check validity of RTC value:
e.g. a value of 5Ah is an invalid value for RTC minute
2. Load CMOS settings into BIOS stack. If CMOS checksum fails, use default value
instead