HP 349239-B21 Serial ATA technology, 2nd edition - Page 3

Serial ATA technology, increasingly difficult to keep the data and clock signals aligned. In addition - target

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After the introduction of parallel ATA, its data transfer rate increased from 3 megabytes per second (MB/s) to 133 MB/s (Figure 2). ATA 100 and ATA 133 have the headroom to handle the sustained transfer rate of today's 7,200-RPM hard disk drives (HDDs) because the interface has to accommodate only one drive at a time. Figure 2. Data transfer rates for parallel ATA modes vs. the sustained transfer rate (STR) of HDDs This performance graph questions the need to change to a serial interface if ATA 100 can handle the requirements of desktop class (5400-RPM and 7200-RPM) HDDs. The answer concerns signaling voltage and data reliability. Parallel ATA data transfer is based on transistor-to-transistor logic (TTL) signaling. TTL signals define an 8-bit digital value, through a sequence of high and low voltage states, on pins 2 through 9 of the parallel port at a given point in time. TTL uses 5V-tolerant, 3.3V signaling, which requires integrated circuits that can tolerate input signals up to 5 volts. It is becoming increasingly difficult to support the traditional 5V TTL signal requirement because components are being fabricated with finer and more fragile lithographies. With regard to data reliability, ATA uses cyclic redundancy checking (CRC) to verify the accuracy of the data signals transmitted between the host and HDD controller. However, ATA command signals are not checked with CRC, so they remain a potential source of error. It would be very difficult to increase the speed of ATA beyond 133 MB/s due to the 5V signaling requirement and the increased likelihood of issues with the integrity of command signals. With parallel bus architectures, the data and clock signals are transmitted along parallel wires from the initiator to the target device at a specific signaling rate. As the signaling rate increases, it becomes increasingly difficult to keep the data and clock signals aligned. In addition, signal integrity is degraded by the electrical noise that results from switching all data signals at the same time. Serial ATA technology Serial ATA discards the parallel ATA Master/Slave concept and only allows one device per cable, which the system views as a master ATA device. These point-to-point connections allow each drive to communicate with the controller without having to wait for other data traffic to clear first. SATA addresses the electrical signaling and signal integrity issues that inhibit increasing the speed of parallel ATA beyond ATA 133. SATA technology has the potential to shrink form factors, lower power consumption, and extend I/O performance to meet the bandwidth requirements of a new wave of technological advances. 3

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After the introduction of parallel ATA, its data transfer rate increased from 3 megabytes per second
(MB/s) to 133 MB/s (Figure 2). ATA 100 and ATA 133 have the headroom to handle the sustained
transfer rate of today's 7,200-RPM hard disk drives (HDDs) because the interface has to
accommodate only one drive at a time.
Figure 2.
Data transfer rates for parallel ATA modes vs. the sustained transfer rate (STR) of HDDs
This performance graph questions the need to change to a serial interface if ATA 100 can handle the
requirements of desktop class (5400-RPM and 7200-RPM) HDDs. The answer concerns signaling
voltage and data reliability. Parallel ATA data transfer is based on transistor-to-transistor logic (TTL)
signaling. TTL signals define an 8-bit digital value, through a sequence of high and low voltage states,
on pins 2 through 9 of the parallel port at a given point in time. TTL uses 5V-tolerant, 3.3V signaling,
which requires integrated circuits that can tolerate input signals up to 5 volts. It is becoming
increasingly difficult to support the traditional 5V TTL signal requirement because components are
being fabricated with finer and more fragile lithographies.
With regard to data reliability, ATA uses cyclic redundancy checking (CRC) to verify the accuracy of
the data signals transmitted between the host and HDD controller. However, ATA command signals
are not checked with CRC, so they remain a potential source of error.
It would be very difficult to increase the speed of ATA beyond 133 MB/s due to the 5V signaling
requirement and the increased likelihood of issues with the integrity of command signals. With
parallel bus architectures, the data and clock signals are transmitted along parallel wires from the
initiator to the target device at a specific signaling rate. As the signaling rate increases, it becomes
increasingly difficult to keep the data and clock signals aligned. In addition, signal integrity is
degraded by the electrical noise that results from switching all data signals at the same time.
Serial ATA technology
Serial ATA discards the parallel ATA Master/Slave concept and only allows one device per cable,
which the system views as a master ATA device. These point-to-point connections allow each drive to
communicate with the controller without having to wait for other data traffic to clear first. SATA
addresses the electrical signaling and signal integrity issues that inhibit increasing the speed of
parallel ATA beyond ATA 133. SATA technology has the potential to shrink form factors, lower
power consumption, and extend I/O performance to meet the bandwidth requirements of a new
wave of technological advances.
3