HP 349239-B21 Serial ATA technology, 2nd edition - Page 4

Low voltage differential signaling SATA technology transmits signals in a single stream rather than in multiple parallel streams. SATA incorporates an low voltage differential (LVD) signaling scheme that uses two pairs of data lines to transmit and receive low-voltage signals (250 mV). The data is represented by the voltage potential between the two wires in each pair (Figure 3). Because it takes less time to apply low voltages to the wires, LVD signaling can occur at a much greater speed than in parallel ATA. The low voltage reduces the effects of capacitance, inductance, and noise. Noise sources tend to add the same amount of voltage to both wires, so the voltage difference between the wires remains the same. Figure 3. LVD signaling Signal integrity Serial architectures encode (embed) the clock signals into the data stream, thus eliminating the skew problem with aligning data and clock signals. Serial architectures require significantly fewer data lines to switch simultaneously, which reduces the introduction of electrical noise. As a result, serial signaling rates can be increased well beyond those attainable with a parallel bus. Serial communication requires a device to convert parallel data into a serial bit stream and vice versa. This device, called a serializer/deserializer (SerDes), contains a parallel digital interface, First-In-First-Out (FIFO) caches, 8 bit/10 bit (8b/10b) encoder and decoder, a serializer, and a deserializer (see Figure 4). The 8b/10b encoder converts each 8-bit data byte to a 10-bit transmission character, which enables clocking information to be encoded into the data stream. Although this adds about 20 percent embedded overhead to the data stream, it eliminates the clock skew problem experienced by parallel ATA. Figure 4. The SerDes core integrates 8b/10b coding and decoding logic. 4