HP X Class 500/550MHz HP Visualize X-Class 500MHz, 550MHz Technical Reference - Page 45

Hot Bus, Intel Pentium III Xeon Processor

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System Board Hot Bus Hot Bus The Host bus of the Pentium III Xeon processors, also referred to as the FSB (Front Side Bus), is implemented in the AGTL (Assisted Gunning Transceiver Logic)+ technology. This technology features open-drain signal drivers that are pulled-up to 1.5 V through resistors at bus extremities; these resistors also act as bus terminators, and are integrated in the processor. If only one processor is installed, a terminating board must be installed in the second processor slot. The supported operating frequencies of the AGTL+ bus is 100 MHz. The width of the data bus is 64 bits, while the width of the address is 32 bits. The control signals of the Host bus allow the implementation of a "split -transaction" bus protocol. This allows the Pentium III Xeon processor to send its request (for example, for the contents of a given memory address) and then to release the bus, rather than waiting for the result, thereby allowing it to accept another request. The Intel 440GX, as target device, then requests the bus again when it is ready to respond, and sends the requested data packet. Up to four transactions are allowed to be outstanding at any given time. For the Host bus to run at 100 MHz while respecting the specified signal and timings, a distributed mechanism is used on each AGTL+ signal. The following termination resistors are used: 150 ohm on the system board (close to the 440GX), 85 ohm on the system board between the two processor slots. The bus is routed with a star topology. Intel Pentium III Xeon Processor The Pentium III Xeon processor has several features that enhance performance: • Single Edge Contact Cartridge (S.E.C.C) package technology first introduced on the Pentium II processor. This packaging technology allows Pentium III Xeon processors to implement the Dual Independent Bus Architecture and have up to 2 MB of level 2 cache. Note that like the Pentium Pro and Pentium II Xeon processors, level 2 cache communication occurs at the full speed of the processor core. • MMX™ technology instructions, which gives enhanced media and communication performance. • Streaming SIMD Extensions for enhanced floating point and 3D application performance. The Pentium III Xeon processor (core and cache memory) is packaged in a self-contained Single Edge Contact (SEC) cartridge installed in a Slot 2 processor slot. The SEC cartridge requires a 330-contact Slot 2 connector on the system board. It includes a processor chip, tag and data SRAMS, and AGTL+ termination resistors, SMBus ROM, and SMBus thermal sensing device. The Pentium III Xeon processor requires two different voltages to supply the CPU core and L2 cache. Each processor codes through Voltage Identification (VID) pins with the required voltage level being 1.8 to 3.5V. Two VID sets are provided, one for the CPU core, and one for the L2 cache. Each VID set is decoded by a Voltage Regulation Module (VRM), installed in a VRM socket on the system board, which supplies the required power voltage to the processor. Chapter 2 45

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Chapter 2
45
System Board
Hot Bus
Hot Bus
The Host bus of the Pentium III Xeon processors, also referred to as the FSB (Front Side
Bus), is implemented in the AGTL (Assisted Gunning Transceiver Logic)+ technology. This
technology features open-drain signal drivers that are pulled-up to 1.5 V through resistors
at bus extremities; these resistors also act as bus terminators, and are integrated in the
processor. If only one processor is installed, a terminating board must be installed in the
second processor slot.
The supported operating frequencies of the AGTL+ bus is 100 MHz. The width of the data
bus is 64 bits, while the width of the address is 32 bits.
The control signals of the Host bus allow the implementation of a “split -transaction” bus
protocol. This allows the Pentium III Xeon processor to send its request (for example, for
the contents of a given memory address) and then to release the bus, rather than waiting
for the result, thereby allowing it to accept another request. The Intel 440GX, as target
device, then requests the bus again when it is ready to respond, and sends the requested
data packet. Up to four transactions are allowed to be outstanding at any given time.
For the Host bus to run at 100 MHz while respecting the specified signal and timings, a
distributed mechanism is used on each AGTL+ signal. The following termination resistors
are used: 150 ohm on the system board (close to the 440GX), 85 ohm on the system board
between the two processor slots. The bus is routed with a star topology.
Intel Pentium III Xeon Processor
The Pentium III Xeon processor has several features that enhance performance:
•
Single Edge Contact Cartridge (S.E.C.C) package technology first introduced on the
Pentium II processor. This packaging technology allows Pentium III Xeon processors to
implement the Dual Independent Bus Architecture and have up to 2 MB of level 2
cache. Note that like the Pentium Pro and Pentium II Xeon processors, level 2 cache
communication occurs at the full speed of the processor core.
•
MMX™ technology instructions, which gives enhanced media and communication
performance.
•
Streaming
SIMD
Extensions
for
enhanced
floating
point
and
3D
application
performance.
The Pentium III Xeon processor (core and cache memory) is packaged in a self-contained
Single Edge Contact (SEC) cartridge installed in a Slot 2 processor slot. The SEC cartridge
requires a 330-contact Slot 2 connector on the system board. It includes a processor chip,
tag and data SRAMS, and AGTL+ termination resistors, SMBus ROM, and SMBus
thermal sensing device.
The Pentium III Xeon processor requires two different voltages to supply the CPU core and
L2 cache. Each processor codes through Voltage Identification (VID) pins with the required
voltage level being 1.8 to 3.5V. Two VID sets are provided, one for the CPU core, and one
for the L2 cache. Each VID set is decoded by a Voltage Regulation Module (VRM), installed
in a VRM socket on the system board, which supplies the required power voltage to the
processor.