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Hitachi IC25N040ATMR04-0 Specifications - Page 53

V Power, DMACK, DMARQ, HDMARDY- Ultra DMA, HSTROBE Ultra DMA, STOP Ultra DMA, DDMARDY- Ultra DMA,

UPC - 407061052632

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extend the PIO cycle. This line can be connected to the host IORDY signal in order to insert a WAIT state(s) into the host PIO cycle. This signal is an Open-Drain output with 16mA sink capability. 5V Power There are two input pins for the +5 V power supply. One is the "+5 V Logic" input pin and the second is the "+5 V Motor" input pin. These two input pins are tied together within the drive. DMACKThis signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted, or that data is available. This signal is internally pulled up to 5 Volt through a 15kW resistor with a resistor tolerance value of -50% to +100%. DMARQ This signal is used for DMA data transfers between the host and drive. It shall be asserted by the drive when it is ready to transfer data to or from the host. The direction of data transfer is controlled by HIOR- and HIOWsignals. This signal is used in a handshake mode with DMACK-. This signal is a 3-state line with 16mA sink capability and internally pulled down to GND through a 10 kW resistor. HDMARDY- (Ultra DMA) This signal is used only for Ultra DMA data transfers between host and drive. The signal HDMARDY- is a flow control signal for Ultra DMA data in bursts. This signal is held asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in transfers. The host may negate HDMARDY- to pause an Ultra DMA data in transfer. HSTROBE (Ultra DMA) This signal is used only for Ultra DMA data transfers between host and drive. The signal HSTROBE is the data out strobe signal from the host for an Ultra DMA data out transfer. Both the rising and falling edge of HSTROBE latch the data from DD (15:0) into the device. The host may stop toggling HSTROBE to pause an Ultra DMA data out transfer. STOP (Ultra DMA) This signal is used only for Ultra DMA data transfers between host and drive. The STOP signal shall be asserted by the host prior to initiation of an Ultra DMA burst. A STOP shall be negated by the host before data is transferred in an Ultra DMA burst. Assertion of STOP by the host during or after data transfer in an Ultra DMA mode signals the termination of the burst. DDMARDY- (Ultra DMA) This signal is used only for Ultra DMA data transfers between host and drive. The signal DDMARDY- is a flow control signal for Ultra DMA data out bursts. This signal is held asserted by the device to indicate to the host that the device is ready to receive Ultra DMA data out transfers. The device may negate DDMARDY- to pause an Ultra DMA data out transfer. DSTROBE (Ultra DMA) This signal is used only for Ultra DMA data transfers between host and drive. The signal DSTROBE is the data in strobe signal from the device for an Ultra DMA data in transfer. Both the rising and the falling edge of DSTROBE latch the data from DD (15:0) into the host. The device may stop toggling DSTROBE to pause an Ultra DMA data in transfer. Travelstar 80GN Hard Disk Drive Specification 43

Section	Page
1.0 General	15
1.1 Introduction	15
1.2 References	15
1.3 Abbreviations	15
1.4 Caution	17
1.5 Drive handling precautions	18
2.0 Outline of the drive	19
3.0 Fixed-disk subsystem description	23
3.1 Control electronics	23
3.2 Head disk assembly data	23
4.0 Drive characteristics	25
4.1 Formatted capacity	25
4.2 Data sheet	25
4.3 Cylinder allocation	26
4.4 Performance characteristics	27
4.4.1 Command overhead	27
4.4.2 Mechanical positioning	27
4.4.3 Operating modes	29
5.0 Data integrity	31
5.1 Data loss at power off	31
5.2 Write Cache	31
5.3 Equipment status	31
5.4 WRITE safety	32
5.5 Data buffer test	32
5.6 Error recovery	32
5.7 Automatic reallocation	32
5.8 ECC	33
6.0 Specification	35
6.1 Environment	35
6.1.1 Temperature and humidity	35
6.1.2 Radiation noise	36
6.1.3 Conductive noise	37
6.1.4 Magnetic fields	37
6.2 DC power requirements	37
6.2.1 Power consumption efficiency	38
6.3 Reliability	38
6.3.1 Data Reliability	38
6.3.2 Failure prediction (S.M.A.R.T.)	38
6.3.3 Cable noise interference	38
6.3.4 Service life and usage condition	39
6.3.5 Preventive maintenance	39
6.3.6 Load/unload	39
6.4 Mechanical specifications	41
6.4.1 Physical dimensions and weight	41
6.4.2 Mounting hole locations	42
6.4.3 Connector and jumper description	42
6.4.4 Mounting orientation	43
6.4.5 Load/unload mechanism	43
6.5 Vibration and shock	43
6.5.1 Operating vibration	43
6.5.2 Nonoperating vibration	44
6.5.3 Operating shock	44
6.5.4 Nonoperating shock	45
6.6 Acoustics	45
6.6.1 Sound power levels	45
6.6.2 Discrete tone penalty	46
6.7 Identification labels	46
6.8 Electromagnetic compatibility	46
6.8.1 CE mark	46
6.8.2 C-TICK mark	46
6.8.3 BSMI mark	46
6.8.4 MIC mark	47
6.9 Safety	47
6.9.1 UL and CSA approval	47
6.9.2 IEC compliance	47
6.9.3 German safety mark	47
6.9.4 Flammability	47
6.9.5 Secondary circuit protection	47
6.10 Packaging	47
7.0 Electrical interface specification	49
7.1 Cabling	49
7.2 Interface connector	49
7.3 Signal definitions	50
7.4 Signal descriptions	51
7.5 Interface logic signal levels	54
7.6 Reset timings	54
7.7 PIO timings	55
7.8 Multi word DMA timings	56
7.9 Ultra DMA timings	57
7.9.1 Initiating Read DMA	57
7.9.2 Host Pausing Read DMA	58
7.9.3 Host Terminating Read DMA	59
7.9.4 Device Terminating Read DMA	60
7.9.5 Initiating Write DMA	61
7.9.6 Device Pausing Write DMA	62
7.9.7 Device Terminating Write DMA	63
7.9.8 Host Terminating Write DMA	64
7.10 Drive address setting	65
7.11 Addressing of HDD registers	66
8.0 General	69
8.1 Introduction	69
8.2 Terminology	69
9.0 Deviations from standard	71
10.0 Register	73
10.1 Alternate Status Register	74
10.2 Command Register	74
10.3 Data Register	74
10.4 Device Control Register	75
10.5 Drive Address Register	75
10.6 Device/Head Register	76
10.7 Error Register	76
10.8 Features Register	77
10.9 LBA High Register	77
10.10 LBA Mid Register	77
10.11 Sector Count Register	77
10.12 Status Register	77
11.0 General	79
11.1 Reset response	79
11.2 Register initialization	80
11.3 Diagnostic and Reset considerations	81
11.4 Power-off considerations	82
11.4.1 Load/Unload	82
11.4.2 Emergency unload	82
11.4.3 Required power-off sequence	82
11.5 Sector Addressing Mode	83
11.5.1 Logical CHS addressing mode	83
11.5.2 LBA addressing mode	83
11.6 Power management features	84
11.6.1 Power mode	84
11.6.2 Power management commands	84
11.6.3 Standby/Sleep command completion time	84
11.6.4 Standby timer	85
11.6.5 Status	85
11.6.6 Interface capability for power modes	85
11.6.7 Initial Power Mode at Power On	85
11.7 Advanced Power Management (ABLE-3) feature	85
11.7.1 Performance Idle Mode	86
11.7.2 Active Idle Mode	86
11.7.3 Low Power Idle Mode	86
11.7.4 Transition time	86
11.8 S.M.A.R.T. Function	87
11.8.1 Attributes	87
11.8.2 Attribute values	87
11.8.3 Attribute thresholds	87
11.8.4 Threshold exceeded condition	87
11.8.5 S.M.A.R.T. commands	87
11.8.6 S.M.A.R.T. operation with power management modes	88
11.9 Security Mode Feature Set	88
11.9.1 Security mode	88
11.9.2 Security level	88
11.9.3 Password	89
11.9.4 Master Password Revision Code	89
11.9.5 Command table	92
11.10 Protected Area Function	93
11.10.1 Example for operation (In LBA Mode)	93
11.10.2 Set Max security extension commands	94
11.11 Address Offset Feature (vendor specific)	95
11.11.1 Enable/Disable Address Offset Mode	95
11.11.2 Identify Device Data	96
11.11.3 Exceptions in Address Offset Mode	96
11.12 Seek Overlap	97
11.13 Write Cache function	97
11.14 Reassign Function	98
11.14.1 Auto Reassign Function	98
11.15 48-bit Address Feature Set	99
12.0 Command protocol	101
12.1 Data In commands	101
12.2 Data Out Commands	102
12.3 Non-data commands	103
12.4 DMA Data Transfer commands:	105
13.0 Command descriptions	107
13.1 Check Power Mode (E5h/98h)	111
13.2 Device Configuration Overlay (B1h)	112
13.2.1 DEVICE CONFIGURATION RESTORE (subcommand C0h)	112
13.2.2 DEVICE CONFIGURATION FREEZE LOCK (subcommand C1h)	112
13.2.3 DEVICE CONFIGURATION IDENTIFY (subcommand C2h)	113
13.2.4 DEVICE CONFIGURATION SET (subcommand C3h)	113
13.3 Execute Device Diagnostic (90h)	115
13.4 Flush Cache (E7h)	116
13.5 Flush Cache EXT (EAh)	117
13.6 Format Track (50h: vendor specific)	118
13.7 Format Unit (F7h: vendor specific)	119
13.8 Identify Device (ECh)	120
13.9 Idle (E3h/97h)	129
13.10 Idle Immediate (E1h/95h)	130
13.11 Initialize Device Parameters (91h)	132
13.12 Read Buffer (E4h)	133
13.13 Read DMA (C8h/C9h)	134
13.14 Read DMA EXT (25h)	136
13.15 Read Long (22h/23h)	138
13.16 Read Multiple (C4h)	140
13.17 Read Multiple EXT (29h)	142
13.18 Read Native Max ADDRESS (F8h)	143
13.19 Read Native Max ADDRESS EXT (27h)	144
13.20 Read Sectors (20h/21h)	145
13.21 Read Sector(s) EXT (24h)	146
13.22 Read Verify Sectors (40h/41h)	148
13.23 Ready Verify Sector(s) EXT (42h)	150
13.24 Recalibrate (1xh)	152
13.25 Security Disable Password (F6h)	153
13.26 Security Disable Password (F6h)	154
13.27 Security Erase Unit (F4h)	155
13.28 Security Freeze Lock (F5h)	157
13.29 Security Set Password (F1h)	158
13.30 Security Unlock (F2h)	160
13.31 Seek (7xh)	161
13.32 Sense Condition (F0h: vendor specific)	162
13.33 Set Features (EFh)	163
13.34 Set Max ADDRESS (F9h)	165
13.35 Set Max ADDRESS EXT (37h)	167
13.36 Set Multiple (C9h)	169
13.37 Sleep (E6h/99h)	170
13.38 S.M.A.R.T. Function Set (B0h)	171
13.38.1 S.M.A.R.T. Function Subcommands	172
13.38.2 Device Attribute Data Structure	176
13.38.3 Device Attribute Thresholds data structure	181
13.38.4 S.M.A.R.T. error log sector	182
13.38.5 Self-test log data structure	184
13.38.6 Error reporting	185
13.39 Standby (E2h/96h)	186
13.40 Standby Immediate (E0h/94h)	187
13.41 Write Buffer (E8h)	188
13.42 Write DMA (CAh/CBh)	189
13.43 Write DMA EXT (35h)	191
13.44 Write Long (32h/33h)	193
13.45 Write Multiple (C5h)	195
13.46 Write Multiple EXT (39h)	196
13.47 Write Sectors (30h/31h)	198
13.48 Write Sectors(s) EXT (34h)	200
13.49 Write Verify (3Ch: vendor specific)	201
14.0 Time-out values	203
15.0 Appendix	205
15.1 Commands Support Coverage	205
15.2 SET FEATURES Commands Support Coverage	207
15.3 Changes from Travelstar 60GH and 40GN	208
A	211
B	211
C	211
D	211
E	211
F	211
H	211
I	211
L	211
M	211
N	212
O	212
P	212
R	212
S	212
T	212
U	212
V	213
W	213

Match case Limit results 1 per page

Travelstar 80GN Hard Disk Drive Specification

extend the PIO cycle. This line can be connected to the host IORDY signal in order to insert a WAIT state(s)

into the host PIO cycle. This signal is an Open-Drain output with 16mA sink capability.

5V Power

There are two input pins for the +5 V power supply. One is the "+5 V Logic" input pin and the second is the "+5

V Motor" input pin. These two input pins are tied together within the drive.

DMACK-

This signal shall be used by the host in response to DMARQ to either acknowledge that data has been accepted,

or that data is available.

This signal is internally pulled up to 5 Volt through a 15kW resistor with a resistor tolerance value of –50% to

+100%.

DMARQ

This signal is used for DMA data transfers between the host and drive. It shall be asserted by the drive when it

is ready to transfer data to or from the host. The direction of data transfer is controlled by HIOR- and HIOW-

signals. This signal is used in a handshake mode with DMACK-. This signal is a 3-state line with 16mA sink

capability and internally pulled down to GND through a 10 kW resistor.

HDMARDY- (Ultra DMA)

This signal is used only for Ultra DMA data transfers between host and drive. The signal HDMARDY- is a flow

control signal for Ultra DMA data in bursts. This signal is held asserted by the host to indicate to the device that

the host is ready to receive Ultra DMA data in transfers. The host may negate HDMARDY- to pause an Ultra

DMA data in transfer.

HSTROBE (Ultra DMA)

This signal is used only for Ultra DMA data transfers between host and drive.

The signal HSTROBE is the data out strobe signal from the host for an Ultra DMA data out transfer. Both the

rising and falling edge of HSTROBE latch the data from DD (15:0) into the device. The host may stop toggling

HSTROBE to pause an Ultra DMA data out transfer.

STOP (Ultra DMA)

This signal is used only for Ultra DMA data transfers between host and drive.

The STOP signal shall be asserted by the host prior to initiation of an Ultra DMA burst. A STOP shall be

negated by the host before data is transferred in an Ultra DMA burst. Assertion of STOP by the host during or

after data transfer in an Ultra DMA mode signals the termination of the burst.

DDMARDY- (Ultra DMA)

This signal is used only for Ultra DMA data transfers between host and drive.

The signal DDMARDY- is a flow control signal for Ultra DMA data out bursts. This signal is held asserted by

the device to indicate to the host that the device is ready to receive Ultra DMA data out transfers. The device

may negate DDMARDY- to pause an Ultra DMA data out transfer.

DSTROBE (Ultra DMA)

This signal is used only for Ultra DMA data transfers between host and drive.

The signal DSTROBE is the data in strobe signal from the device for an Ultra DMA data in transfer. Both the

rising and the falling edge of DSTROBE latch the data from DD (15:0) into the host. The device may stop tog-

gling DSTROBE to pause an Ultra DMA data in transfer.