IBM DTLA-307075 Hard Drive Specifications - Page 37

DD0-DD15 DA0-DA2 CS0CS1RESETDIOWDIORINTRQ IOCS16DASP- PDIAG- 16-bit bi-directional data bus between the host and the drive. The lower 8 lines, DD00-07, are used for Register and ECC access. All 16 lines, DD00-15, are used for data transfer. These are 3-State lines with 24 mA current sink capability. Address used to select the individual register in the drive. Chip select signal generated from the Host address bus. When active, one of the Command Block Registers (Data, Error {Features when written}, Sector Count, Sector Number, Cylinder Low, Cylinder High, Drive/Head and Status {Command when written} register) can be selected. (See Figure 42 on page 0.) Chip select signal generated from the Host address bus. When active one of the Control Block Registers (Alternate Status {Device Control when written} and Drive Address register) can be selected. (See Figure 42 on page 0.) This line is used to reset the drive. It shall be kept in Low logic state during power up and in High thereafter. The strobe signal asserted by the host to write device registers or the data port. The strobe signal asserted by the host to read device registers or the data port. Interrupt is enabled only when the drive is selected and the host activates the nIEN bit in the Device Control Reg. Otherwise, this signal is in high impedance state regardless of the state of the IRQ bit. The interrupt is set when the IRQ bit is set by the drive CPU. IRQ is reset to zero by a host read of the status register or a write to the Command Reg. This signal is a 3-State line with 24 mA sink capability. Indication to the host that a 16-bit wide data register has been addressed and that the drive is prepared to send or receive a 16-bit wide data word. This signal is an Open-drain output with 24 mA sink capability and an external resistor is needed to pull this line to 5 volts. This is a time-multiplexed signal which indicates that a drive is active, or that device 1 is present. This signal is driven by Open-Drain driver and internally pulled-up to 5 volts through a 10kΩ resistor. During Power-on initialization or after RESET- is negated, DASP- shall be asserted by Device 1 within 400 ms to indicate that device 1 is present. Device 0 shall allow up to 450 ms for device 1 to assert DASP-. If device 1 is not present, device 0 may assert DASPto drive an LED indicator. DASP- shall be negated following acceptance of the first valid command by device 1. Anytime after negation of DASP-, either drive may assert DASP- to indicate that a drive is active. PDIAG- shall be asserted by device 1 to indicate to device 0 that it has completed diagnostics. This line is pulled-up to 5 volts in the drive through a 10kΩ resistor. Following a Power On Reset, software reset, or RESET-, drive 1 shall negate PDIAGwithin 1 ms (to indicate to device 0 that it is busy). Drive 1 shall then assert PDIAGwithin 30 seconds to indicate that it is no longer busy and is able to provide status. Following the receipt of a valid Execute Drive Diagnostics command, device 1 shall negate PDIAG- within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics. If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for drive 1 to assert PDIAG-. Device 1 should clear BSY before asserting PDIAG-, as PDIAG- is used to indicate that device 1 has passed its diagnostics and is ready to post status. Deskstar 40GV & 75GXP hard disk drive specifications 25