Intel D525MW Product Specification - Page 70

Intel Desktop Board D525MW and Intel Desktop Board D525MWV Technical Product Specification Table 41. Port 80h POST Codes POST Code 10 11 12 13 Description of POST Operation Host Processor Power-on initialization of the host processor (Boot Strap Processor) Host processor cache initialization (including APs) Starting Application processor initialization SMM initialization Chipset 21 Initializing a chipset component Memory 22 23 24 25 26 27 28 Reading SPD from memory DIMMs Detecting presence of memory DIMMs Programming timing parameters in the memory controller and the DIMMs Configuring memory Optimizing memory settings Initializing memory, such as ECC init Testing memory PCI Bus 50 51 52 53 - 57 Enumerating PCI busses Allocating resources to PCI bus Hot Plug PCI controller initialization Reserved for PCI Bus USB 58 59 Resetting USB bus Reserved for USB ATA/ATAPI/SATA 5A 5B Resetting PATA/SATA bus and all devices Reserved for ATA SMBus 5C 5D Resetting SMBus Reserved for SMBus Local Console 70 71 72 Resetting the VGA controller Disabling the VGA controller Enabling the VGA controller Remote Console 78 79 7A Resetting the console controller Disabling the console controller Enabling the console controller continued 70