Intel DP55KG Product Guide - Page 76

Table 17. Port 80h POST Codes, PEI Phase Before MRC - overclocking

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Intel Desktop Board DP55KG Product Guide Table 17 lists the Port 80h POST codes in hexadecimal notation. Table 17. Port 80h POST Codes POST Code Description 00 01-05 10, 20, 30, 40, 50 ACPI S States Entering S0 state, standard Entering S1-S5 state Resuming from S1-S5 state 08 09 0A, 0B 0C 0D 0E 0F Security Phase (SEC) Starting BIOS execution after CPU BIST SPI prefetching and caching Load BSP/APS microcode Platform program base addresses Wake up all APS Initialize NEM Pass entry point of the PEI core 11 12 13 14 15 16 17, 18 19, 1A 1B, 1C PEI Phase Before MRC Set bootmode, GPIO init Early chipset register programming Basic PCH init, discrete device init LAN init Exit early platform init driver SMBUS driver init Entry/Exit to SMBUS execute read/write Entry/Exit to CK505 programming Entry/Exit to PEI overclock programming MEC Memory Detection 21 MRC entry point 23 Reading SPD from memory DIMMs 24 Detecting presence of memory DIMMs 27 Configuring memory 28 Testing memory 29 Exit MRC driver 2A, 2B PEI After MRC Start/finish programming MTRR settings 31, 33, 34 PEIMs/Recovery Recovery has initiate, load, valid 76

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Intel Desktop Board DP55KG Product Guide
76
Table 17 lists the Port 80h POST codes in hexadecimal notation.
Table 17. Port 80h POST Codes
POST Code
Description
ACPI S States
00
Entering S0 state, standard
01-05
Entering S1-S5 state
10, 20, 30,
40, 50
Resuming from S1-S5 state
Security Phase (SEC)
08
Starting BIOS execution after CPU BIST
09
SPI prefetching and caching
0A, 0B
Load BSP/APS microcode
0C
Platform program base addresses
0D
Wake up all APS
0E
Initialize NEM
0F
Pass entry point of the PEI core
PEI Phase Before MRC
11
Set bootmode, GPIO init
12
Early chipset register programming
13
Basic PCH init, discrete device init
14
LAN init
15
Exit early platform init driver
16
SMBUS driver init
17, 18
Entry/Exit to SMBUS execute read/write
19, 1A
Entry/Exit to CK505 programming
1B, 1C
Entry/Exit to PEI overclock programming
MEC Memory Detection
21
MRC entry point
23
Reading SPD from memory DIMMs
24
Detecting presence of memory DIMMs
27
Configuring memory
28
Testing memory
29
Exit MRC driver
PEI After MRC
2A, 2B
Start/finish programming MTRR settings
PEIMs/Recovery
31, 33, 34
Recovery has initiate, load, valid