Intel E6420 Data Sheet

Intel E6420 - Core 2 Duo Dual-Core Processor Manual

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  • Intel E6420 | Data Sheet - Page 1
    Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequences Datasheet -on 65 nm Process in the 775-land LGA Package and supporting Intel® 64 Architecture and supporting Intel® Virtualization Technology± October 2007 Document Number: 313278-007
  • Intel E6420 | Data Sheet - Page 2
    system delivers Execute Disable Bit functionality. The Intel® Core™2 Duo desktop processor E6000 and E4000 sequences and Intel® Core™2 Extreme processor X6800 may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Contact your local
  • Intel E6420 | Data Sheet - Page 3
    1 Introduction ...11 1.1 Terminology ...12 1.1.1 Processor Terminology 12 1.2 References ...14 2 Electrical Specifications 15 2.1 Power and Ground Lands 15 2.2 Decoupling Guidelines 15 2.2.1 VCC Decoupling 15 2.2.2 Vtt Decoupling 15 2.2.3 FSB Decoupling 16 2.3 Voltage Identification 16
  • Intel E6420 | Data Sheet - Page 4
    103 7.2.1 Fan Heatsink Power Supply 103 7.3 Thermal Specifications 105 7.3.1 Boxed Processor Cooling Requirements 105 7.3.2 Fan Speed Control Operation (Intel® Core2 Extreme Processor X6800 Only 107 7.3.3 Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor E6000 and E4000 Sequences
  • Intel E6420 | Data Sheet - Page 5
    Clock Crosspoint Specification 34 8 Processor Package Assembly Sketch 37 9 Processor Package Drawing Sheet 1 of 3 38 10 Processor Package Drawing Sheet 2 of 3 39 11 Processor Package Drawing Sheet 3 of 3 40 12 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processor E6000
  • Intel E6420 | Data Sheet - Page 6
    27 Processor Thermal Specifications 80 28 Thermal Profile (Intel® Core™2 Duo Desktop Processor E6x50 Sequence and E6540 with 4 MB L2 Cache 81 29 Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache)...82 30 Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500
  • Intel E6420 | Data Sheet - Page 7
    (Intel® Core2 Duo Desktop Processor E6000 and E4000 Sequences Only) • Added Intel® Core™2 Duo Desktop Processor E6420, E6320, and E4400 information • Added Intel® Core™2 Duo Desktop Processor E6850, E6750, E6550, E6540, and E4500 information. • Added specifications for 1333 MHz FSB. • Added support
  • Intel E6420 | Data Sheet - Page 8
    8 Datasheet
  • Intel E6420 | Data Sheet - Page 9
    made between performance and power consumption. The Intel Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000, E4000 sequence also include the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable
  • Intel E6420 | Data Sheet - Page 10
    § § 10 Datasheet
  • Intel E6420 | Data Sheet - Page 11
    Execute Disable Bit, Intel® 64 architecture, and Enhanced Intel SpeedStep® Technology. The Intel Core™2 Duo desktop processor E6000 sequence and Intel Core™2 Extreme processor X6800 support Intel® Virtualization Technology (Intel VT). In addition, the Intel Core™2 Duo desktop processors E6850, E6750
  • Intel E6420 | Data Sheet - Page 12
    processors, memory, and I/O. Processor Terminology Commonly used terms are explained here for clarification: • Intel® Core™2 Extreme processor X6800 - Dual core processor in the FCLGA6 package with a 4 MB L2 cache. • Intel® Core™2 Duo desktop processor E6850, E6750, E6550, E6540, E6700, E6600, E6420
  • Intel E6420 | Data Sheet - Page 13
    trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support). • Intel® Virtualization Technology (Intel VT) - Intel Virtualization Technology provides silicon-based functionality that works
  • Intel E6420 | Data Sheet - Page 14
    Documents Document Location Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update www.intel.com/design/ processor/specupdt/ 313279.htm Intel® Core™2 Duo Processor and Intel® Pentium® Dual Core Processor Thermal and Mechanical
  • Intel E6420 | Data Sheet - Page 15
    for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 5. Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large
  • Intel E6420 | Data Sheet - Page 16
    to the Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence and Intel® Core™2 Extreme Processor X6800 Specification Update for further details on specific valid core frequency and VID values of the processor. Note this differs from the VID employed by the processor during a power management
  • Intel E6420 | Data Sheet - Page 17
    Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 VID4 VID3 VID2 VID1 VID (V) 1 1 1 1 0 1 0.8500 1 1 1 1 0 0 0.8625 1 1 1 0 1 1 0.8750 1 1 1 0 1 0 0.8875 1 1 1 0 0 1 0.9000 1 1 1 0 0 0 0.9125 1 1 0 1 1 1 0.9250 1 1 0
  • Intel E6420 | Data Sheet - Page 18
    MSID1 MSID0 Description 0 0 Intel® Core™2 Duo desktop processor E6000 and E4000 sequence and the Intel® Core™2 Extreme processor X6800 0 1 Reserved 1 must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for
  • Intel E6420 | Data Sheet - Page 19
    between 40 Ω and 60 Ω should be used. Voltage and Current Specification Absolute Maximum and Minimum Ratings Table 4 specifies absolute maximum and minimum ratings or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric
  • Intel E6420 | Data Sheet - Page 20
    Electrical Specifications Table 4. 2.6.2 Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes1, 2 VCC Core voltage with respect to VSS -0.3 1.55 V - VTT FSB termination voltage with respect to VSS -0.3 1.55 V - TC Processor case temperature See See Chapter
  • Intel E6420 | Data Sheet - Page 21
    current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket to determine the total ITT drawn by the
  • Intel E6420 | Data Sheet - Page 22
    circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification is required to ensure
  • Intel E6420 | Data Sheet - Page 23
    for overshoot allowed as shown in Section 2.6.3. 2. This loadline specification shows the deviation from the VID set point. 3. The processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket
  • Intel E6420 | Data Sheet - Page 24
    circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification is required to ensure
  • Intel E6420 | Data Sheet - Page 25
    overshoot allowed as shown in Section 2.6.3. 2. This loadline specification shows the deviation from the VID set point. 3. The Processor Power Delivery Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR implementation details. VCC Overshoot The processor can
  • Intel E6420 | Data Sheet - Page 26
    power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel
  • Intel E6420 | Data Sheet - Page 27
    Specifications 2.7.1 Table 9. FSB CMOS Open Drain Output Open Drain Input/ Output FSB Clock Clock Power/Other ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# A20M#, IGNNE#, INIT 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug
  • Intel E6420 | Data Sheet - Page 28
    Electrical Specifications . Table 10. . Table 11. 2.7.2 Signal Characteristics Signals with RTT A[35:3]#, ADS#, ADSTB are required to be asserted/deasserted for at least four BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC. See Section 6.2
  • Intel E6420 | Data Sheet - Page 29
    Table 13. Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. GTL+ Signal Group DC Specifications Symbol Parameter Min
  • Intel E6420 | Data Sheet - Page 30
    90 25.15 Ω 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. GTLREF is to be generated from VTT by a output driver. 4. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for
  • Intel E6420 | Data Sheet - Page 31
    on the processor clocking, contact your Intel Field representative. Platforms using a CK505 Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8. Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications in Section 2.7.9. Core Frequency to FSB
  • Intel E6420 | Data Sheet - Page 32
    H L FSB Frequency 266 MHz RESERVED RESERVED 200 MHz RESERVED RESERVED RESERVED 333 MHz Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 5 for DC specifications. BCLK[1:0] Specifications (CK505
  • Intel E6420 | Data Sheet - Page 33
    CROSS Median - 75 mV CLK 1 VCROSS Max 550 mV VCROSS Min 300 mV High Time Low Time Period VCROSS median Figure 5. Differential Clock Crosspoint Specification Crossing Point (mV) 650 600 550 500 550 + 0.5 (VHavg - 700) 450 550 mV 400 300 + 0.5 (VHavg - 700) 350 300 300 mV 250 200 660
  • Intel E6420 | Data Sheet - Page 34
    Margin 0.200 N/A N/A V 4 8 VTM Threshold Region VCROSS - 0.100 N/A VCROSS + 0.100 V 4 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of
  • Intel E6420 | Data Sheet - Page 35
    of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/ fan speed control. More detailed information is available in the Platform Environment Control Interface (PECI) Specification. PECI DC
  • Intel E6420 | Data Sheet - Page 36
    Electrical Specifications 36 Datasheet
  • Intel E6420 | Data Sheet - Page 37
    Package Mechanical Specifications 3 Package Mechanical Specifications Figure 8. The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An
  • Intel E6420 | Data Sheet - Page 38
    Figure 9. Processor Package Drawing Sheet 1 of 3 Package Mechanical Specifications 38 Datasheet
  • Intel E6420 | Data Sheet - Page 39
    Package Mechanical Specifications Figure 10. Processor Package Drawing Sheet 2 of 3 Datasheet 39
  • Intel E6420 | Data Sheet - Page 40
    Figure 11. Processor Package Drawing Sheet 3 of 3 Package Mechanical Specifications 40 Datasheet
  • Intel E6420 | Data Sheet - Page 41
    package. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket. 4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement
  • Intel E6420 | Data Sheet - Page 42
    . The diagrams are to aid in the identification of the processor. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache with 1333 MHz FSB INTEL M ©'05 E6850 INTEL® CORE™2 DUO SLxxx [COO] 3.00GHZ/4M/1333/06 [FPO] e4 ATPO S/N 42 Datasheet
  • Intel E6420 | Data Sheet - Page 43
    Package Mechanical Specifications Figure 13. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 4 MB L2 Cache with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6700 SLxxx [COO] 2.66GHZ/4M/1066/06 [FPO] e4 ATPO S/N Figure 14. Processor Top-Side
  • Intel E6420 | Data Sheet - Page 44
    Specifications Figure 15. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E4000 Sequence with 2 MB L2 Cache INTEL M ©'05 E4500 INTEL® CORE™2 DUO SLxxx [COO] 2.20GHZ/2M/800/06 [FPO] e4 ATPO S/N Figure 16. E E Processor Top-Side Markings for the Intel® Core
  • Intel E6420 | Data Sheet - Page 45
    Package Mechanical Specifications 3.1.8 Processor Land Coordinates . Figure 17. Figure 17 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. Processor Land Coordinates and Quadrants (Top View) V CC / V SS
  • Intel E6420 | Data Sheet - Page 46
    Package Mechanical Specifications 46 Datasheet
  • Intel E6420 | Data Sheet - Page 47
    and Signal Descriptions 4 4.1 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 18 and Figure 19. These
  • Intel E6420 | Data Sheet - Page 48
    Land Listing and Signal Descriptions Figure 18. land-out Diagram (Top View - Left Side) 30 29 28 27 26 25 24 23 22 21 20 AN VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS AM VCC AL VCC AK VSS AJ VSS AH VCC AG VCC AF VSS AE VSS AD VCC AC VCC AB VSS AA VSS
  • Intel E6420 | Data Sheet - Page 49
    Land Listing and Signal Descriptions Figure 19. 14 13 VCC VSS VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VSS land-out Diagram (Top View - Right Side) 12 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS 11 VCC VCC VCC VCC VCC VCC VCC VCC VCC 10 VSS VSS VSS
  • Intel E6420 | Data Sheet - Page 50
    /Output G8 Common Clock Input F3 Common Clock Input/Output G29 Power/Other Output H30 Power/Other Output G30 Power/Other Output A13 Power/Other Input T1 Power/Other Input G2 Power/Other Input R1 Power/Other Input B13 Power/Other Input B4 Source Synch Input/Output C5 Source Synch
  • Intel E6420 | Data Sheet - Page 51
    Power/Other J2 Power/Other T2 Power/Other F2 Power/Other AK6 Power/Other E24 Power/Other H29 Power/Other Y3 Power/Other AE3 Power/Other E5 Power/Other F6 Power/Other J3 Power/Other A24 Power/Other E29 Power/Other G1 Power/Other U1 Power/Other U2 Power/Other U3 Power/Other J16 Power
  • Intel E6420 | Data Sheet - Page 52
    Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction FC33 FC34 FC35 FC36 FC37 H16 J17 H4 AD3 AB3 Power/Other Power/Other Power/Other Power/Other Power/Other FC38 FC38 FC39 FC40 FERR#/PBE# GTLREF0 GTLREF1 HIT# HITM# IERR# IGNNE# INIT# ITP_CLK0 ITP_CLK1 LINT0 LINT1 LOCK
  • Intel E6420 | Data Sheet - Page 53
    VCC VCC AF22 Power/Other AF8 Power/Other AF9 Power/Other AG11 Power/Other AG12 Power/Other AG14 Power/Other AG15 Power/Other AG18 Power/Other AG19 Power/Other AG21 Power/Other AG22 Power/Other AG25 Power/Other AG26 Power/Other AG27 Power/Other AG28 Power/Other AG29 Power/Other AG30 Power/Other AG8
  • Intel E6420 | Data Sheet - Page 54
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E6420 | Data Sheet - Page 55
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E6420 | Data Sheet - Page 56
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E6420 | Data Sheet - Page 57
    AG23 Power/Other AG24 Power/Other AG7 Power/Other AH1 Power/Other AH10 Power/Other AH13 Power/Other AH16 Power/Other AH17 Power/Other AH20 Power/Other AH23 Power/Other AH24 Power/Other AH3 Power/Other AH6 Power/Other AH7 Power/Other AJ10 Power/Other AJ13 Power/Other AJ16 Power/Other AJ17 Power/Other
  • Intel E6420 | Data Sheet - Page 58
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E6420 | Data Sheet - Page 59
    V7 W4 Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E6420 | Data Sheet - Page 60
    /Other Source Synch Input/Output Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Common Clock Input Source
  • Intel E6420 | Data Sheet - Page 61
    Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Common Clock Input/Output Power/Other Common Clock Input/Output Power/Other Power/Other Source Synch Input/Output Source Synch Input
  • Intel E6420 | Data Sheet - Page 62
    Power/Other Clock Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E6420 | Data Sheet - Page 63
    Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other FC31 Power/Other FC34 Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC Power/Other VCC
  • Intel E6420 | Data Sheet - Page 64
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other 64
  • Intel E6420 | Data Sheet - Page 65
    W7 VSS Power/Other W8 VCC Power/Other W23 VCC Power/Other W24 VCC Power/Other W25 VCC Power/Other W26 VCC Power/Other W27 VCC Power/Other W28 VCC Power/Other W29 VCC Power/Other W30 VCC Power/Other Y1 FC0 Power/Other Y2 VSS Power/Other Y3 FC17 Power/Other Y4
  • Intel E6420 | Data Sheet - Page 66
    Power/Other Power/Other Power/Other Power/Other Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E6420 | Data Sheet - Page 67
    Input/Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other
  • Intel E6420 | Data Sheet - Page 68
    /Output Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E6420 | Data Sheet - Page 69
    /Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power/Other Power
  • Intel E6420 | Data Sheet - Page 70
    bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the
  • Intel E6420 | Data Sheet - Page 71
    to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active ( BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID
  • Intel E6420 | Data Sheet - Page 72
    64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts DRDY# to indicate the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may
  • Intel E6420 | Data Sheet - Page 73
    event functionality, including the identification of support of the feature and enable/disable information, refer to volume 3 of the Intel Architecture Software Developer's Manual and the Intel Processor Identification and the CPUID Instruction application note. Input GTLREF[1:0] determine the
  • Intel E6420 | Data Sheet - Page 74
    and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set
  • Intel E6420 | Data Sheet - Page 75
    de-asserts PROCHOT#. See Section 5.2.4 for more details. PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. 'Clean' implies that the signal will remain low (capable of
  • Intel E6420 | Data Sheet - Page 76
    , causes the processor to enter a low power Stop-Grant state. The processor issues a StopGrant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units. The processor continues to snoop bus transactions and service interrupts while
  • Intel E6420 | Data Sheet - Page 77
    ) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed following Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. Output VID[7:0] (Voltage ID) signals are used to support automatic selection of power supply
  • Intel E6420 | Data Sheet - Page 78
    PLLs. VSS_SENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure Processor Power Delivery Design Guidelines For Desktop LGA775 Socket. Miscellaneous voltage supply. The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply
  • Intel E6420 | Data Sheet - Page 79
    the fan speed only need to ensure the case temperature meets the thermal profile specifications. To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate
  • Intel E6420 | Data Sheet - Page 80
    to the "Component Identification Information" section power of the Ianntedl®TCC. ore™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update for processor specific Idle power. 4. 775_VR_CONFIG_06/775_VR_CONFIG_05B guidelines provide
  • Intel E6420 | Data Sheet - Page 81
    Thermal Specifications and Design Considerations Table 28. Thermal Profile (Intel® Core™2 Duo Desktop Processor E6x50 Sequence and E6540 with 4 MB L2 Cache) Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power Maximum Tc (°C) 0 44.7 2 45.5 4 46.4 6 47.2 8 48.1 10 48.9 12 49.7
  • Intel E6420 | Data Sheet - Page 82
    Specifications and Design Considerations Table 29. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache) Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power 59.3 64 59.8 65 60.1 Figure 21. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000
  • Intel E6420 | Data Sheet - Page 83
    Thermal Specifications and Design Considerations Table 30. Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L2 Cache) Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power Maximum Tc (°C) 0 45.3 2 46.2 4 47.0 6 47.9 8 48.7 10 49.6 12 50.5 14 51.3
  • Intel E6420 | Data Sheet - Page 84
    Specifications and Design Considerations Table 31. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence with 2 MB L2 Cache) Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power .6 64 61.1 65 61.4 Figure 23. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000
  • Intel E6420 | Data Sheet - Page 85
    Thermal Specifications and Design Considerations Table 32. Thermal Profile (Intel® Core™2 Extreme Processor X6800) Power (W) Maximum Tc (°C) Power Maximum Tc (°C) Power 0 43.2 26 49.2 52 2 43.7 28 49.6 54 4 44.1 30 50.1 56 6 44.6 32 50.6 58 8 45.0 34 51.0 60 10 45.5
  • Intel E6420 | Data Sheet - Page 86
    reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must be enabled for the processor to be operating within specifications. The temperature at which Thermal
  • Intel E6420 | Data Sheet - Page 87
    drivers, or interrupt handling routines. Thermal Monitor 2 The processor also supports an additional power reduction capability known as Thermal Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor
  • Intel E6420 | Data Sheet - Page 88
    of this mechanism to limit the processor temperature. If bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand
  • Intel E6420 | Data Sheet - Page 89
    signal when the processor (either core) has reached its maximum operating temperature or be power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power Processor Power Delivery Design Guidelines For Desktop LGA775 Socket
  • Intel E6420 | Data Sheet - Page 90
    temperature specification based on a temperature reading from the thermal diode. The value for TCONTROL will be calibrated in manufacturing and configured for each processor Intel does not support or recommend operation of the thermal diode under reverse bias. 2. Characterized across a temperature
  • Intel E6420 | Data Sheet - Page 91
    Thermal Specifications and Design Considerations temperature (Kelvin). 6. The series resistance, RT, provided in the Diode Model Table (Table 33) can be used for more accurate readings as needed. The processor does not support the diode correction offset that exists on other Intel processors
  • Intel E6420 | Data Sheet - Page 92
    speed control solutions based on PECI uses a TCONTROL value stored in the processor IA32_TEMPERATURE_TARGET MSR. The TCONTROL MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the TCONTROL value as negative. Thermal management
  • Intel E6420 | Data Sheet - Page 93
    Thermal Specifications and Design Considerations . Figure 28. Conceptual Fan Control on PECI-Based Platforms Fan Speed (RPM) TCONTROL Setting TCC Activation Temperature Max PECI = -10 PECI = 0 Min PECI = -20 Temperature Note: Not intended to depict actual implementation . Figure 29.
  • Intel E6420 | Data Sheet - Page 94
    socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification. PECI Command Support PECI command support is covered in detail in the Platform Environment Control Interface Specification client processor device if valid temperature readings
  • Intel E6420 | Data Sheet - Page 95
    handled by configuring the EXT_CONFIG Model Specific Register (MSR). This MSR will allow for the disabling of a single core. 6.2 Clock Control and Low Power States The processor allows the use of AutoHALT and Stop Grant states to reduce power consumption by stopping the clock to internal sections
  • Intel E6420 | Data Sheet - Page 96
    . HALT and Extended HALT Powerdown States The processor supports the HALT or Extended HALT powerdown state. The Extended HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification. The Extended HALT state is a lower power state as compared to the Stop Grant
  • Intel E6420 | Data Sheet - Page 97
    via the BIOS. When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended HALT Powerdown state must be enabled via the BIOS for the processor to remain within its specification. The processor
  • Intel E6420 | Data Sheet - Page 98
    processors are capable of supporting Enhanced Intel SpeedStep® Technology. More details on which processor frequencies support this feature is provided in the Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence and Intel® Core™2 Extreme Processor X6800 Specification Update. Enhanced Intel
  • Intel E6420 | Data Sheet - Page 99
    are key features of Enhanced Intel SpeedStep® Technology: • Multiple voltage/frequency operating points provide optimal performance at reduced power consumption. • Voltage/frequency selection is software controlled by writing to processor MSRs (Model Specific Registers), thus eliminating chipset
  • Intel E6420 | Data Sheet - Page 100
    Features 100 Datasheet
  • Intel E6420 | Data Sheet - Page 101
    Boxed Processor Specifications 7 Boxed Processor Specifications The processor is also offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling
  • Intel E6420 | Data Sheet - Page 102
    Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink. Figure 31 shows a mechanical representation of the boxed processor. Figure 32. Clearance is required around the fan
  • Intel E6420 | Data Sheet - Page 103
    V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the baseboard. The power cable connector and pinout are shown in Figure 35. Baseboards must provide a matched power header to support the boxed processor. Table 38 contains specifications
  • Intel E6420 | Data Sheet - Page 104
    Processor Specifications Figure 35. The boxed processor's fanheat sink requires a constant +12 V supplied to pin 2 and does not support variable voltage control or 3-pin PWM control. The power header on the baseboard must be positioned to allow the fan heatsink power cable to reach it. The power
  • Intel E6420 | Data Sheet - Page 105
    Boxed Processor Specifications Figure 36. Baseboard Power Header Placement Relative to Processor Socket R110 [4.33] B C 7.3 7.3.1 Boxed Proc PwrHeaderPlacement Thermal Specifications This section describes the cooling requirements of the fan heatsink solution used by the boxed processor. Boxed
  • Intel E6420 | Data Sheet - Page 106
    Boxed Processor Specifications Figure 37. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) Figure 38. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View) 106 Datasheet
  • Intel E6420 | Data Sheet - Page 107
    4 Processor, Intel® Core™2 Duo Extreme Processor X6800 Thermal and Mechanical Design Guidelines. The Internal chassis temperature should be kept below 39 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. The motherboard must supply
  • Intel E6420 | Data Sheet - Page 108
    Point Highest Noise Level Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature (Degrees C) Table 39. Fan Heatsink Power and Signal Specifications Boxed Processor Fan Heatsink Set Point (°C) Boxed Processor Fan Speed Notes X ≤ 30 Y = 35 Z ≥ 38 When the internal chassis
  • Intel E6420 | Data Sheet - Page 109
    designs. Under thermistor controlled mode, the fan RPM is automatically varied based on the Tinlet temperature measured by a thermistor located at the fan inlet. For more details on specific motherboard requirements for 4-wire based fan speed control, refer to the appropriate Thermal and Mechanical
  • Intel E6420 | Data Sheet - Page 110
    Boxed Processor Specifications 110 Datasheet
  • Intel E6420 | Data Sheet - Page 111
    Processor Specifications 8 Balanced Technology Extended (BTX) Boxed Processor Specifications The processor is offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from largely standard components. The boxed processor will be supplied
  • Intel E6420 | Data Sheet - Page 112
    shape and size will remain the same. Mechanical Specifications Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions This section documents the mechanical specifications of the boxed processor TMA. The boxed processor will be shipped with an unattached TMA
  • Intel E6420 | Data Sheet - Page 113
    Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 42. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes NOTE: Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation. Datasheet 113
  • Intel E6420 | Data Sheet - Page 114
    Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 43. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume 8.1.2 NOTE: Diagram does not show the attached hardware for the clip
  • Intel E6420 | Data Sheet - Page 115
    Extended (BTX) Boxed Processor Specifications 8.1.3 Boxed Processor Support and Retention Module (SRM) Figure 44. The boxed processor TMA requires an SRM assembly provided by the chassis manufacturer. The SRM provides the attach points for the TMA and provides structural support for the board by
  • Intel E6420 | Data Sheet - Page 116
    Balanced Technology Extended (BTX) Boxed Processor Specifications 8.2 Electrical Requirements 8.2.1 Thermal Module Assembly Power Supply The boxed processor's Thermal Module Assembly (TMA) requires a +12 V power supply. The TMA will include power cable to power the integrated fan and will plug
  • Intel E6420 | Data Sheet - Page 117
    Balanced Technology Extended (BTX) Boxed Processor Specifications Table 40. TMA Power and Signal Specifications Description +12V: 12 volt fan power supply IC: - Peak Fan current draw - Fan start-up current draw - Fan start-up current draw maximum duration Min 10.2 - - - Typ 12 1.0 - - Max 13.8
  • Intel E6420 | Data Sheet - Page 118
    47 and Table 41. The internal chassis temperature should be kept below 35.5 ºC. Meeting the processor's temperature specification (see Chapter 5) is the responsibility of the system integrator. The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of
  • Intel E6420 | Data Sheet - Page 119
    Balanced Technology Extended (BTX) Boxed Processor Specifications Figure 47. Boxed Processor TMA Set Points Increasing Fan Speed & Noise Higher Set Point Highest Noise Level Lower Set Point Lowest Noise Level X Y Z Internal Chassis Temperature (Degrees C) Table 41. TMA Set Points for 3-wire
  • Intel E6420 | Data Sheet - Page 120
    Balanced Technology Extended (BTX) Boxed Processor Specifications the motherboard that sends out a PWM control signal to the 4th pin of the connector labeled as CONTROL. The fan speed is based on a combination of actual processor temperature and thermistor temperature. If the 4-wire PWM controlled
  • Intel E6420 | Data Sheet - Page 121
    the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a system that can make use of an LAI: mechanical and electrical. Mechanical Considerations The LAI is installed between the processor socket and the processor. The LAI lands plug into
  • Intel E6420 | Data Sheet - Page 122
    Debug Tools Specifications 122 Datasheet
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Document Number: 313278-007
Intel
®
Core™2 Extreme Processor
X6800
Δ
and Intel
®
Core™2 Duo
Desktop Processor E6000
Δ
and
E4000
Δ
Sequences
Datasheet
—on 65 nm Process in the 775-land LGA Package and supporting Intel
®
64
Architecture and supporting Intel
®
Virtualization Technology
±
October 2007