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Land Listing and Signal Descriptions

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Land Listing and Signal Descriptions Table 24. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction D22# D23# D24# D25# D26# D27# D28# D29# D30# D31# D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D44# D45# D46# D47# D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D10 F11 F12 D13 E13 G13 F14 G14 F15 G15 G16 E15 E16 G18 G17 F17 F18 E18 E19 F20 E21 F21 G21 E22 D22 G22 D20 D17 A14 C15 C14 B15 C18 B16 A17 B18 C21 B21 B19 Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Source Synch Input/Output Table 24. Alphabetical Land Assignments Land Name Land Signal Buffer # Type Direction D61# D62# D63# DBI0# DBI1# DBI2# DBI3# DBR# DBSY# DEFER# DRDY# DSTBN0# DSTBN1# DSTBN2# DSTBN3# DSTBP0# DSTBP1# DSTBP2# DSTBP3# FC0 FC3 FC4 FC5 FC8 FC10 FC15 FC17 FC18 FC20 FC21 FC22 FC23 FC26 FC27 FC28 FC29 FC30 FC31 FC32 A19 Source Synch Input/Output A22 Source Synch Input/Output B22 Source Synch Input/Output A8 Source Synch Input/Output G11 Source Synch Input/Output D19 Source Synch Input/Output C20 Source Synch Input/Output AC2 Power/Other Output B2 Common Clock Input/Output G7 Common Clock Input C1 Common Clock Input/Output C8 Source Synch Input/Output G12 Source Synch Input/Output G20 Source Synch Input/Output A16 Source Synch Input/Output B9 Source Synch Input/Output E12 Source Synch Input/Output G19 Source Synch Input/Output C17 Source Synch Input/Output Y1 Power/Other J2 Power/Other T2 Power/Other F2 Power/Other AK6 Power/Other E24 Power/Other H29 Power/Other Y3 Power/Other AE3 Power/Other E5 Power/Other F6 Power/Other J3 Power/Other A24 Power/Other E29 Power/Other G1 Power/Other U1 Power/Other U2 Power/Other U3 Power/Other J16 Power/Other H15 Power/Other Datasheet 51

Section	Page
Contents	3
Figures	5
Tables	6
Revision History	7
Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Features	9
1 Introduction	11
1.1 Terminology	12
1.1.1 Processor Terminology	12
1.2 References	14
Table 1. Reference Documents	14
2 Electrical Specifications	15
2.1 Power and Ground Lands	15
2.2 Decoupling Guidelines	15
2.2.1 VCC Decoupling	15
2.2.2 Vtt Decoupling	15
2.2.3 FSB Decoupling	16
2.3 Voltage Identification	16
Table 2. Voltage Identification Definition	17
2.4 Market Segment Identification (MSID)	18
Table 3. Market Segment Selection Truth Table for MSID[1:0], , ,	18
2.5 Reserved, Unused, and TESTHI Signals	18
2.6 Voltage and Current Specification	19
2.6.1 Absolute Maximum and Minimum Ratings	19
Table 4. Absolute Maximum and Minimum Ratings	20
2.6.2 DC Voltage and Current Specification	20
Table 5. Voltage and Current Specifications	20
Table 6. VCC Static and Transient Tolerance for Processors with 4 MB L2 Cache	22
Figure 1. VCC Static and Transient Tolerance for Processors with 4 MB L2 Cache	23
Table 7. VCC Static and Transient Tolerance for Processors with 2 MB L2 Cache	24
Figure 2. VCC Static and Transient Tolerance for Processors with 2 MB L2 Cache	25
2.6.3 VCC Overshoot	25
Table 8. VCC Overshoot Specifications	25
Figure 3. VCC Overshoot Example Waveform	26
2.6.4 Die Voltage Validation	26
2.7 Signaling Specifications	26
2.7.1 FSB Signal Groups	27
Table 9. FSB Signal Groups	27
Table 10. Signal Characteristics	28
Table 11. Signal Reference Voltages	28
2.7.2 CMOS and Open Drain Signals	28
2.7.3 Processor DC Specifications	29
Table 12. GTL+ Signal Group DC Specifications	29
Table 13. Open Drain and TAP Output Signal Group DC Specifications	29
Table 14. CMOS Signal Group DC Specifications	30
2.7.3.1 GTL+ Front Side Bus Specifications	30
Table 15. GTL+ Bus Voltage Definitions	30
2.7.4 Clock Specifications	31
2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking	31
Table 16. Core Frequency to FSB Multiplier Configuration	31
2.7.6 FSB Frequency Select Signals (BSEL[2:0])	31
Table 17. BSEL[2:0] Frequency Table for BCLK[1:0]	32
2.7.7 Phase Lock Loop (PLL) and Filter	32
2.7.8 BCLK[1:0] Specifications (CK505 based Platforms)	32
Table 18. Front Side Bus Differential BCLK Specifications	32
Figure 4. Differential Clock Waveform	33
Figure 5. Differential Clock Crosspoint Specification	33
Figure 6. Differential Measurements	33
2.7.9 BCLK[1:0] Specifications (CK410 based Platforms)	34
Table 19. Front Side Bus Differential BCLK Specifications	34
Figure 7. Differential Clock Crosspoint Specification	34
2.8 PECI DC Specifications	35
Table 20. PECI DC Electrical Limits	35
3 Package Mechanical Specifications	37
Figure 8. Processor Package Assembly Sketch	37
3.1 Package Mechanical Drawing	37
Figure 9. Processor Package Drawing Sheet 1 of 3	38
Figure 10. Processor Package Drawing Sheet 2 of 3	39
Figure 11. Processor Package Drawing Sheet 3 of 3	40
3.1.1 Processor Component Keep-Out Zones	41
3.1.2 Package Loading Specifications	41
Table 21. Processor Loading Specifications	41
3.1.3 Package Handling Guidelines	41
Table 22. Package Handling Guidelines	41
3.1.4 Package Insertion Specifications	42
3.1.5 Processor Mass Specification	42
3.1.6 Processor Materials	42
Table 23. Processor Materials	42
3.1.7 Processor Markings	42
Figure 12. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache with 1333 MHz FSB	42
Figure 13. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 4 MB L2 Cache with 1066 MHz FSB	43
Figure 14. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 2 MB L2 Cache	43
Figure 15. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E4000 Sequence with 2 MB L2 Cache	44
Figure 16. Processor Top-Side Markings for the Intel® Core™2 Extreme Processor X6800	44
3.1.8 Processor Land Coordinates	45
Figure 17. Processor Land Coordinates and Quadrants (Top View)	45
4 Land Listing and Signal Descriptions	47
4.1 Processor Land Assignments	47
Figure 18. land-out Diagram (Top View - Left Side)	48
Figure 19. land-out Diagram (Top View - Right Side)	49
Table 24. Alphabetical Land Assignments	50
Table 25. Numerical Land Assignment	60
4.2 Alphabetical Signals Reference	70
Table 26. Signal Description (Sheet 1 of 9)	70
5 Thermal Specifications and Design Considerations	79
5.1 Processor Thermal Specifications	79
5.1.1 Thermal Specifications	79
Table 27. Processor Thermal Specifications	80
Table 28. Thermal Profile (Intel® Core™2 Duo Desktop Processor E6x50 Sequence and E6540 with 4 MB L2 Cache)	81
Figure 20. Thermal Profile (Intel® Core™2 Duo Desktop Processor E6x50 Sequence and E6540 with 4 MB L2 Cache)	81
Table 29. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache)	82
Figure 21. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache)	82
Table 30. Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L2 Cache)	83
Figure 22. Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L2 Cache)	83
Table 31. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence with 2 MB L2 Cache)	84
Figure 23. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence with 2 MB L2 Cache)	84
Table 32. Thermal Profile (Intel® Core™2 Extreme Processor X6800)	85
Figure 24. Thermal Profile (Intel® Core™2 Extreme Processor X6800)	85
5.1.2 Thermal Metrology	86
Figure 25. Case Temperature (TC) Measurement Location	86
5.2 Processor Thermal Features	86
5.2.1 Thermal Monitor	86
5.2.2 Thermal Monitor 2	87
Figure 26. Thermal Monitor 2 Frequency and Voltage Ordering	88
5.2.3 On-Demand Mode	88
5.2.4 PROCHOT# Signal	89
5.2.5 THERMTRIP# Signal	89
5.3 Thermal Diode	90
Table 33. Thermal “Diode” Parameters using Diode Model	90
Table 34. Thermal “Diode” Parameters using Transistor Model	91
Table 35. Thermal Diode Interface	91
5.4 Platform Environment Control Interface (PECI)	92
5.4.1 Introduction	92
Figure 27. Processor PECI Topology	92
5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management	92
Figure 28. Conceptual Fan Control on PECI-Based Platforms	93
Figure 29. Conceptual Fan Control on Thermal Diode-Based Platforms	93
5.4.2 PECI Specifications	94
5.4.2.1 PECI Device Address	94
5.4.2.2 PECI Command Support	94
5.4.2.3 PECI Fault Handling Requirements	94
5.4.2.4 PECI GetTemp0() Error Code Support	94
Table 36. GetTemp0() Error Codes	94
6 Features	95
6.1 Power-On Configuration Options	95
Table 37. Power-On Configuration Option Signals	95
6.2 Clock Control and Low Power States	95
Figure 30. Processor Low Power State Machine	96
6.2.1 Normal State	96
6.2.2 HALT and Extended HALT Powerdown States	96
6.2.2.1 HALT Powerdown State	96
6.2.2.2 Extended HALT Powerdown State	97
6.2.3 Stop Grant and Extended Stop Grant States	97
6.2.3.1 Stop Grant State	97
6.2.3.2 Extended Stop Grant State	98
6.2.4 Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State	98
6.2.4.1 HALT Snoop State, Stop Grant Snoop State	98
6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State	98
6.3 Enhanced Intel® SpeedStep® Technology	98
7 Boxed Processor Specifications	101
Figure 31. Mechanical Representation of the Boxed Processor	101
7.1 Mechanical Specifications	102
7.1.1 Boxed Processor Cooling Solution Dimensions	102
Figure 32. Space Requirements for the Boxed Processor (Side View)	102
Figure 33. Space Requirements for the Boxed Processor (Top View)	102
Figure 34. Space Requirements for the Boxed Processor (Overall View)	103
7.1.2 Boxed Processor Fan Heatsink Weight	103
7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly	103
7.2 Electrical Requirements	103
7.2.1 Fan Heatsink Power Supply	103
Figure 35. Boxed Processor Fan Heatsink Power Cable Connector Description	104
Table 38. Fan Heatsink Power and Signal Specifications	104
Figure 36. Baseboard Power Header Placement Relative to Processor Socket	105
7.3 Thermal Specifications	105
7.3.1 Boxed Processor Cooling Requirements	105
Figure 37. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)	106
Figure 38. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)	106
7.3.2 Fan Speed Control Operation (Intel® Core2 Extreme Processor X6800 Only)	107
7.3.3 Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor E6000 and E4000 Sequences Only)	107
Figure 39. Boxed Processor Fan Heatsink Set Points	108
Table 39. Fan Heatsink Power and Signal Specifications	108
8 Balanced Technology Extended (BTX) Boxed Processor Specifications	111
Figure 40. Mechanical Representation of the Boxed Processor with a Type I TMA	111
Figure 41. Mechanical Representation of the Boxed Processor with a Type II TMA	112
8.1 Mechanical Specifications	112
8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions	112
Figure 42. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes	113
Figure 43. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume	114
8.1.2 Boxed Processor Thermal Module Assembly Weight	114
8.1.3 Boxed Processor Support and Retention Module (SRM)	115
Figure 44. Assembly Stack Including the Support and Retention Module	115
8.2 Electrical Requirements	116
8.2.1 Thermal Module Assembly Power Supply	116
Figure 45. Boxed Processor TMA Power Cable Connector Description	116
Table 40. TMA Power and Signal Specifications	117
Figure 46. Balanced Technology Extended (BTX) Mainboard Power Header Placement (hatched area)	117
8.3 Thermal Specifications	118
8.3.1 Boxed Processor Cooling Requirements	118
8.3.2 Variable Speed Fan	118
Figure 47. Boxed Processor TMA Set Points	119
Table 41. TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors	119
9 Debug Tools Specifications	121
9.1 Logic Analyzer Interface (LAI)	121
9.1.1 Mechanical Considerations	121

Match case Limit results 1 per page

Land Listing and Signal Descriptions

Datasheet

D22#

D10

Source Synch

Input/Output

D23#

F11

Source Synch

Input/Output

D24#

F12

Source Synch

Input/Output

D25#

D13

Source Synch

Input/Output

D26#

E13

Source Synch

Input/Output

D27#

G13

Source Synch

Input/Output

D28#

F14

Source Synch

Input/Output

D29#

G14

Source Synch

Input/Output

D30#

F15

Source Synch

Input/Output

D31#

G15

Source Synch

Input/Output

D32#

G16

Source Synch

Input/Output

D33#

E15

Source Synch

Input/Output

D34#

E16

Source Synch

Input/Output

D35#

G18

Source Synch

Input/Output

D36#

G17

Source Synch

Input/Output

D37#

F17

Source Synch

Input/Output

D38#

F18

Source Synch

Input/Output

D39#

E18

Source Synch

Input/Output

D40#

E19

Source Synch

Input/Output

D41#

F20

Source Synch

Input/Output

D42#

E21

Source Synch

Input/Output

D43#

F21

Source Synch

Input/Output

D44#

G21

Source Synch

Input/Output

D45#

E22

Source Synch

Input/Output

D46#

D22

Source Synch

Input/Output

D47#

G22

Source Synch

Input/Output

D48#

D20

Source Synch

Input/Output

D49#

D17

Source Synch

Input/Output

D50#

A14

Source Synch

Input/Output

D51#

C15

Source Synch

Input/Output

D52#

C14

Source Synch

Input/Output

D53#

B15

Source Synch

Input/Output

D54#

C18

Source Synch

Input/Output

D55#

B16

Source Synch

Input/Output

D56#

A17

Source Synch

Input/Output

D57#

B18

Source Synch

Input/Output

D58#

C21

Source Synch

Input/Output

D59#

B21

Source Synch

Input/Output

D60#

B19

Source Synch

Input/Output

Table 24.

Alphabetical Land

Assignments

Land Name

Land

Signal Buffer

Type

Direction

D61#

A19

Source Synch

Input/Output

D62#

A22

Source Synch

Input/Output

D63#

B22

Source Synch

Input/Output

DBI0#

Source Synch

Input/Output

DBI1#

G11

Source Synch

Input/Output

DBI2#

D19

Source Synch

Input/Output

DBI3#

C20

Source Synch

Input/Output

DBR#

AC2

Power/Other

Output

DBSY#

Common Clock Input/Output

DEFER#

Common Clock

Input

DRDY#

Common Clock Input/Output

DSTBN0#

Source Synch

Input/Output

DSTBN1#

G12

Source Synch

Input/Output

DSTBN2#

G20

Source Synch

Input/Output

DSTBN3#

A16

Source Synch

Input/Output

DSTBP0#

Source Synch

Input/Output

DSTBP1#

E12

Source Synch

Input/Output

DSTBP2#

G19

Source Synch

Input/Output

DSTBP3#

C17

Source Synch

Input/Output

FC0

Power/Other

FC3

Power/Other

FC4

Power/Other

FC5

Power/Other

FC8

AK6

Power/Other

FC10

E24

Power/Other

FC15

H29

Power/Other

FC17

Power/Other

FC18

AE3

Power/Other

FC20

Power/Other

FC21

Power/Other

FC22

Power/Other

FC23

A24

Power/Other

FC26

E29

Power/Other

FC27

Power/Other

FC28

Power/Other

FC29

Power/Other

FC30

Power/Other

FC31

J16

Power/Other

FC32

H15

Power/Other

Table 24.

Alphabetical Land

Assignments

Land Name

Land

Signal Buffer

Type

Direction